upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 95

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(2) Improvement of performance
High-speed
system clock (f
Internal oscillation
clock (f
RESET
CPU clock
Because the CPU can be started without waiting for the high-speed system clock oscillation stabilization time, the
total performance can be improved.
A timing diagram of the CPU default start using the internal oscillator is shown in Figure 5-12.
Note Check using the oscillation stabilization time counter status register (OSTC). Waiting for the oscillation
(a) When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is set to 0 and the internal
(b) After RESET release, the CPU clock can be switched from the internal oscillation clock to the high-speed
(c) The internal oscillator can be set to stopped/oscillating using the internal oscillation mode register (RCM)
(d) When the internal oscillation clock is used as the CPU clock, the high-speed system clock can be set to
(e) Select the high-speed system clock oscillation stabilization time (2
R
)
oscillation clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks of the
internal oscillation clock have elapsed after RESET release (or clock supply to the CPU stops for 17 clocks).
During the RESET period, oscillation of the high-speed system clock and the internal oscillation clock is
stopped.
system clock using bit 0 (MCM0) of the main clock mode register (MCM) after the high-speed system clock
oscillation stabilization time has elapsed. At this time, check the oscillation stabilization time using the
oscillation stabilization time counter status register (OSTC) before switching the CPU clock. The CPU clock
status can be checked using bit 1 (MCS) of MCM.
when “Can be stopped by software” is selected for the internal oscillator by the option byte, if the high-speed
system clock is used as the CPU clock. Make sure that MCS is 1 at this time.
stopped/oscillating using the main OSC control register (MOC). Make sure that MCS is 0 at this time.
the oscillation stabilization time select register (OSTS) when releasing STOP mode while the high-speed
system clock is being used as the CPU clock. In addition, when releasing STOP mode while RESET is
released and the internal oscillation clock is being used as the CPU clock, check the high-speed system
clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC).
stabilization time is not required when the external RC oscillation clock is selected as the high-speed
system clock by the option byte. Therefore, the CPU clock can be switched without reading the OSTC
value.
XP
)
Figure 5-12. Timing Diagram of CPU Default Start Using Internal Oscillator
Operation
stopped: 17/f
High-speed system clock oscillation stabilization time:
R
2
11
/f
CHAPTER 5 CLOCK GENERATOR
XP
Internal oscillation clock
to 2
User’s Manual U16846EJ3V0UD
16
/f
XP
Note
11
/f
XP
Switched by software
, 2
High-speed system clock
13
/f
XP
, 2
14
/f
XP
, 2
15
/f
XP
, 2
16
/f
XP
) using
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