upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 421

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upd78f0103hmca1-5a4-a

Manufacturer Part Number
upd78f0103hmca1-5a4-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
16-bit
timer/event
counter 00
(TM00)
Function
Details of Function
TOC00: 16-bit
timer output
control register 00
PRM00: Prescaler
mode register 00
CR010: 16-bit
timer
capture/compare
register 010
CR000, CR010:
16-bit timer
capture/compare
registers 000, 010
PPG output
Pulse width
measurement
External event
counter
One-shot pulse
output: Software
trigger
Do not make settings <1> and <2> below simultaneously. In addition, follow the setting
procedure shown below.
<1> Setting of TOC001, TOC004, TOE00, and OSPE00: Setting of timer output operation
<2> Setting of LVS00 and LVR00: Setting of timer output F/F
When the internal oscillation clock is selected as the clock to be supplied to the CPU, the
clock of the internal oscillator is divided and supplied as the count clock. If the count clock
is the internal oscillation clock, the operation of 16-bit timer/event counter 00 is not
guaranteed. When an external clock is used and when the internal oscillation clock is
selected and supplied to the CPU, the operation of 16-bit timer/event counter 00 is not
guaranteed, either, because the internal oscillation clock is supplied as the sampling clock
to eliminate noise.
Always set data to PRM00 after stopping the timer operation.
If the valid edge of the TI000 pin is to be set for the count clock, do not set the clear & start
mode using the valid edge of the TI000 pin and the capture trigger.
If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is
immediately detected after the rising edge or both the rising and falling edges are set as the
valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00
(TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, when
re-enabling operation after the operation has been stopped, the rising edge is not detected
if the TI000 or TI010 pin is high level.
When the TI010 pin valid edge is used, P01 cannot be used as the timer output pin (TO00).
When P01 is used as the TO00 pin, the TI010 pin valid edge cannot be used.
To change the value of the duty factor (the value of the CR010 register) during operation,
see Caution 2 in Figure 6-15 PPG Output Operation Timing.
Values in the following range should be set in CR000 and CR010:
0000H ≤ CR010 < CR000 ≤ FFFFH
The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty
of (CR010 setting value + 1)/(CR000 setting value + 1).
In the PPG output operation, change the pulse width (rewrite CR010) during TM00
operation using the following procedure.
<1> Disable the timer output inversion operation by match of TM00 and CR010
<2> Disable the INTTM010 interrupt (TMMK010 = 1)
<3> Rewrite CR010
<4> Wait for 1 cycle of the TM00 count clock
<5> Enable the timer output inversion operation by match of TM00 and CR010
<6> Clear the interrupt request flag of INTTM010 (TMIF010 = 0)
<7> Enable the INTTM010 interrupt (TMMK010 = 0)
To use two capture registers, set the TI000 and TI010 pins.
When reading the external event counter count value, TM00 should be read.
Do not set the OSPT00 bit to 1 while the one-shot pulse is being output. To output the one-
shot pulse again, wait until the current one-shot pulse output is completed.
When using the one-shot pulse output of 16-bit timer/event counter 00 with a software
trigger, do not change the level of the TI000 pin or its alternate-function port pin.
Because the external trigger is valid even in this case, the timer is cleared and started even
at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a
pulse at an undesired timing.
(TOC004 = 0)
(TOC004 = 1)
APPENDIX D LIST OF CAUTIONS
User’s Manual U16846EJ3V0UD
Cautions
p. 111
p. 113
p. 113
p. 113
p. 113
p. 113
p. 117
p. 118
p. 118
p. 119
p. 120
p. 130
p. 133
p. 133
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