upd78f0730 Renesas Electronics Corporation., upd78f0730 Datasheet - Page 85

• Manufacturer Part Number: upd78f0730
• Description: 8-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

(1) Clock operation mode select register (OSCCTL)
This register selects the operation modes of the high-speed system clock and the gain of the on-chip oscillator.
OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Address: FF9FH
OSCCTL
Symbol
Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency
Remark f
EXCLK
EXCLK
AMPH
Figure 5-2. Format of Clock Operation Mode Select Register (OSCCTL)
<7>
0
0
1
1
0
1
After reset: 00H
XH
2. Set AMPH before setting the peripheral functions after a reset release. The value
3. If the STOP instruction is executed with AMPH set to 1 when the internal high-
4. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7
: High-speed system clock oscillation frequency
f
10 MHz < f
XH
OSCSEL
OSCSEL
exceeds 10 MHz.
of AMPH can be changed only once after a reset release. The clock supply to the
CPU is stopped for 5
speed oscillation clock or external main system clock is used as the CPU clock,
then the clock supply to the CPU is stopped for 5
has been released.
stabilization time is counted after the STOP mode has been released.
(MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or
the external clock from the EXCLK pin is disabled).
≤ 10 MHz
<6>
0
1
0
1
XH
R/W
Preliminary User’s Manual U19014EJ1V0UD
CHAPTER 5 CLOCK GENERATOR
High-speed system clock
I/O port mode
X1 oscillation mode
I/O port mode
External clock input
mode
pin operation mode
0
5
µ
s (MIN.) after AMPH has been set to 1.
If the X1 clock is used as the CPU clock, oscillation
0
4
Operating frequency control
I/O port
Crystal/ceramic resonator connection
I/O port
I/O port
3
0
P121/X1 pin
2
0
µ
s (MIN.) after the STOP mode
External clock input
P122/X2/EXCLK pin
1
0
AMPH
<0>
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