upd78f0730 Renesas Electronics Corporation., upd78f0730 Datasheet - Page 108
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upd78f0730
Manufacturer Part Number
upd78f0730
Description
8-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD78F0730.pdf
(518 pages)
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(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
(2) CPU operating with high-speed system clock (C) after reset release (A)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
Remarks 1.
108
(A) → (B)
Status Transition
(A) → (B) → (C) (X1 clock: f
(A) → (B) → (C)
(A) → (B) → (C) (X1 clock: 10 MHz < f
(A) → (B) → (C)
(external main clock: f
(external main clock: 10 MHz < f
Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers.
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET)).
2.
(Setting sequence of SFR registers)
Status Transition
MSTOP:
XSEL, MCM0:
(A) to (E) in Table 5-4 correspond to (A) to (E) in Figure 5-14.
EXCLK, OSCSEL, AMPH:
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/3)
Setting Flag of SFR Register
XH
≤ 10 MHz)
XH
≤ 10 MHz)
XH
)
Bits 7, 6 and 0 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
XH
)
Preliminary User’s Manual U19014EJ1V0UD
CHAPTER 5 CLOCK GENERATOR
SFR registers do not have to be set (default status after reset release).
AMPH
0
0
1
1
EXCLK
0
1
0
1
OSCSEL
1
1
1
1
SFR Register Setting
MSTOP
0
0
0
0
Must not be
Must not be
checked
checked
Must be
Must be
Register
checked
checked
OSTC
XSEL
1
1
1
1
MCM0
1
1
1
1
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