upd78f0730 Renesas Electronics Corporation., upd78f0730 Datasheet - Page 221

• Manufacturer Part Number: upd78f0730
• Description: 8-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

9.4.2 Setting overflow time of watchdog timer
starts counting again by writing “ACH” to WDTE during the window open period before the overflow time.
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer
The following overflow time is set.
Caution The watchdog timer does not stop during self-programming of the flash memory and
Remarks 1. f
5. The watchdog timer does not stop during self-programming of the flash memory and
WDCS2
depending on the set value of bit 0 (LIOCP) of the option byte.
If LIOCP = 0, the watchdog timer resumes counting after the HALT or STOP mode is released.
At this time, the counter is not cleared to 0 but starts counting from the value at which it was
stopped.
If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the
internal oscillation mode register (RCM) = 1) when LIOCP = 0, the watchdog timer stops
operating. At this time, the counter is not cleared to 0.
EEPROM
overflow time and window size taking this delay into consideration.
In HALT mode
In STOP mode
0
0
0
0
1
1
1
1
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set
the overflow time and window size taking this delay into consideration.
2. ( ): f
RL
TM
: Internal low-speed oscillation clock frequency
WDCS1
Table 9-3. Setting of Overflow Time of Watchdog Timer
emulation. During processing, the interrupt acknowledge time is delayed. Set the
RL
0
0
1
1
0
0
1
1
= 264 kHz (MAX.)
Watchdog timer operation stops.
LIOCP = 0 (Internal Low-Speed Oscillator
Preliminary User’s Manual U19014EJ1V0UD
CHAPTER 9 WATCHDOG TIMER
WDCS0
Can Be Stopped by Software)
0
1
0
1
0
1
0
1
2
2
2
2
2
2
2
2
10
11
12
13
14
15
16
17
/f
/f
/f
/f
/f
/f
/f
/f
RL
RL
RL
RL
RL
RL
RL
RL
(3.88 ms)
(7.76 ms)
(15.52 ms)
(31.03 ms)
(62.06 ms)
(124.12 ms)
(248.24 ms)
(496.48 ms)
Overflow Time of Watchdog Timer
Watchdog timer operation continues.
LIOCP = 1 (Internal Low-Speed Oscillator
Cannot Be Stopped)
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