upd78f0730 Renesas Electronics Corporation., upd78f0730 Datasheet - Page 45
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upd78f0730
Manufacturer Part Number
upd78f0730
Description
8-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD78F0730.pdf
(518 pages)
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Notes 1.
FF73H
FF74H
FF75H
FF76H
FF77H
FF78H
FF79H
FF7AH
FF80H
FF81H
FF84H
FF8BH
FF8CH
FF90H
FF91H
FF92H
FF93H
FF94H
FF95H
FF96H
FF99H
FF9AH
FF9CH
FF9DH
FF9EH
FF9FH
FFA0H
FFA1H
FFA2H
FFA3H
FFA4H
FFA6H
FFA7H
FFACH
FFBAH
FFBBH
FFBCH
Address
2.
3.
UF0 endpoint 1 interface mapping register
UF0 endpoint 2 interface mapping register
UF0 data end register
UF0 EP0 length register
UF0 bulk out 1 length register
UF0 descriptor length register
UF0 FIFO clear 0 register
UF0 FIFO clear 1 register
Serial operation mode register 10
Serial clock selection register 10
Transmit buffer register 10
USB function 0 buffer control register
Timer clock selection register 51
UF0 address register
UF0 configuration register
UF0 interface 0 register
UF0 interface 1 register
UF0 interface 2 register
UF0 interface 3 register
UF0 interface 4 register
Watchdog timer enable register
UF0 device status register
UF0 EP0 status register
UF0 EP1 status register
UF0 EP2 status register
Clock operation mode select register
Internal oscillation mode register
Main clock mode register
Main OSC control register
Oscillation stabilization time counter status register OSTC
Oscillation stabilization time select register
PLL control register
USB clock control register
Reset control flag register
16-bit timer mode control register 00
Prescaler mode register 00
Capture/compare control register 00
The reset value of WDTE is determined by setting of option byte.
The value of this register is 00H immediately after a reset release but automatically changes to 80H after
oscillation accuracy stabilization of high-speed internal oscillator has been waited.
The reset value of RESF vary depending on the reset source.
Special Function Register (SFR) Name
Table 3-7. Special Function Register List (3/4)
Preliminary User’s Manual U19014EJ1V0UD
CHAPTER 3 CPU ARCHITECTURE
UF0E1IM
UF0E2IM
UF0DEND
UF0E0L
UF0BO1L
UF0DSCL
UF0FIC0
UF0FIC1
CSIM10
CSIC10
SOTB10
UF0BC
TCL51
UF0ADRS
UF0CNF
UF0IF0
UF0IF1
UF0IF2
UF0IF3
UF0IF4
WDTE
UF0DSTL
UF0E0SL
UF0E1SL
UF0E2SL
OSCCTL
RCM
MCM
MOC
OSTS
PLLC
UCKC
RESF
TMC00
PRM00
CRC00
Symbol
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
R
R
R
R
R
R
R
R
R
1 Bit
Manipulatable Bit Unit
8 Bits
16 Bits
1AH/9AH
80H
00H
Reset
After
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
80H
00H
05H
00H
00H
00H
00H
00H
Note 1
Note 2
Note 3
45
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