upd78f0730 Renesas Electronics Corporation., upd78f0730 Datasheet - Page 427
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upd78f0730
Manufacturer Part Number
upd78f0730
Description
8-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD78F0730.pdf
(518 pages)
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Notes 1.
8-bit timer H1
Watchdog timer
Serial interface UART6
Serial interfaces CSI10
USB function controller
USBF
2.
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
The reset value of WDTE is determined by the option byte setting.
Table 15-2. Hardware Statuses After Reset Acknowledgment (2/3)
Compare registers 01, 11 (CMP01, CMP11)
Mode register (TMHMD1)
Carrier control register 1 (TMCYC1)
Enable register (WDTE)
Receive buffer register 6 (RXB6)
Transmit buffer register 6 (TXB6)
Asynchronous serial interface operation mode register 6 (ASIM6)
Asynchronous serial interface reception error status register 6 (ASIS6)
Asynchronous serial interface transmission status register 6 (ASIF6)
Clock selection register 6 (CKSR6)
Baud rate generator control register 6 (BRGC6)
Transmit buffer register 10 (SOTB10)
Serial I/O shift register 10 (SIO10)
Serial operation mode register 10 (CSIM10)
Serial clock selection register 10 (CSIC10)
UF0 EP0NAK register (UF0E0N)
UF0 EP0NAKALL register (UF0E0NA)
UF0 EPNAK register (UF0EN)
UF0 EPNAK mask register (UF0ENM)
UF0 SNDSIE register (UF0SDS)
UF0 CLR request register (UF0CLR)
UF0 SET request register (UF0SET)
UF0 EP status n register (UF0EPSn) (n = 0 to 2)
UF0 INT status n register (UF0ISn) (n = 0 to 4)
UF0 INT mask n register (UF0IMn) (n = 0 to 4)
UF0 INT clear n register (UF0ICn) (n = 0 to 4)
UF0 FIFO clear n register (UF0FICn) (n = 0, 1)
UF0 data end register (UF0DEND)
UF0 GPR register (UF0GPR)
UF0 mode control register (UF0MODC)
UF0 mode status register (UF0MODS)
UF0 active interface number register (UF0AIFN)
UF0 active alternative setting register (UF0AAS)
UF0 alternative setting status register (UF0ASS)
UF0 endpoint n interface mapping register (UF0EnIM) (n = 1, 2)
UF0 EP0 read register (UF0E0R)
UF0 EP0 length register (UF0E0L)
UF0 EP0 setup register (UF0E0ST)
Preliminary User’s Manual U19014EJ1V0UD
CHAPTER 15 RESET FUNCTION
Hardware
00H
00H
00H
1AH/9AH
FFH
FFH
01H
00H
00H
00H
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
Undefined
00H
00H
Acknowledgment
Status After Reset
Note 2
Note 1
427
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