upd78f0730 Renesas Electronics Corporation., upd78f0730 Datasheet - Page 291

• Manufacturer Part Number: upd78f0730
• Description: 8-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

(8) UF0 EP status 0 register (UF0EPS0)
UF0EPS0
Bit position
This register indicates the USB bus status and the presence or absence of register data.
This register is read-only, in 8-bit units.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 2)
and the current setting of the interface.
It takes five USB clocks to reflect the status on this register after the UF0FIC0 and UF0FIC1 registers have
been set. If it is necessary to read the status correctly, therefore, separate writing to the UF0FIC0 and
UF0FIC1 registers from reading from the UF0EPS0, UF0EPS1, UF0EPS2, UF0E0N, and UF0EN registers by
at least four USB clocks.
4
2
1
0
7
0
BKOUT1
BKIN1
EP0W
EP0R
Bit name
6
0
CHAPTER 12 USB FUNCTION CONTROLLER (USBF)
This bit indicates that data is in the UF0BO1 register (FIFO) connected to the CPU side.
When the FIFO configuring the UF0BO1 register is toggled, this bit is automatically set
to 1 by hardware. It is automatically cleared to 0 by hardware when reading the UF0BO1
register (FIFO) connected to the CPU side has been completed (counter value = 0). It is
not set to 1 when Null data is received (toggling the FIFO does not take place either).
This bit indicates that data is in the UF0BI1 register (FIFO) connected to the CPU side.
By setting the BKI1DED bit of the UF0DEND register to 1, the status in which data is in
the UF0BI1 register can be created even if data is not written to the register (Null data
transmission). As soon as the BKI1DED bit of the UF0DEND register has been set to 1
while the counter of the UF0BI1 register is 0, this bit is set to 1 by hardware. It is cleared
to 0 when a toggle operation is performed.
This bit indicates that data is in the UF0E0W register (FIFO). By setting the E0DED bit
of the UF0DEND register to 1, the status in which data is in the UF0E0W register can be
created even if data is not written to the register (Null data transmission). As soon as the
E0DED bit of the UF0DEND register is set to 1 even when the counter of the UF0E0W
register is 0, this bit is set to 1 by hardware. It is cleared to 0 after correct transmission.
This bit indicates that data is in the UF0E0R register (FIFO). It is automatically cleared
to 0 by hardware when reading the UF0E0R register (FIFO) has been completed
(counter value = 0). It is not set to 1 if Null data is received.
5
0
1: Data is in the register.
0: No data is in the register (default value).
1: Data is in the register.
0: No data is in the register (default value).
1: Data is in the register.
0: No data is in the register (default value).
1: Data is in the register.
0: No data is in the register (default value).
Preliminary User’s Manual U19014EJ1V0UD
BKOUT1
4
3
0
BKIN1
2
Function
EP0W
1
EP0R
0
Address
FF67H
After reset
00H
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