DSP56F807 Motorola Inc, DSP56F807 Datasheet - Page 9

• Manufacturer Part Number: DSP56F807
• Description: 56F807 16-bit Hybrid Processor
• Manufacturer: Motorola Inc

2.4 Address, Data, and Bus Control Signals
56F807 Technical Data
No. of
No. of
Pins
No. of
Pins
Pins
16
6
2
8
1
GPIOE2-
GPIOA0-
GPIOA7
D0–D15
GPIOE3
A8–A15
A0–A5
A6–A7
Signal
Signal
Signal
Name
CLKO
Name
Name
Signal
Output
Input/O
Input/O
Signal
Output
Output
Output
Input/O
Type
Signal
Type
utput
utput
Type
utput
Freescale Semiconductor, Inc.
Table 6. PLL and Clock (Continued)
For More Information On This Product,
State During
Chip-driven
State During
State During
Table 7. Address Bus Signals
Tri-stated
Tri-stated
Tri-stated
Reset
Tri-stated
Reset
Table 8. Data Bus Signals
Reset
Input
Input
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Clock Output—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
Address Bus—A0–A5 specify the address for external
Program or Data memory accesses.
Address Bus—A6–A7 specify the address for external
Program or Data memory accesses.
Port E GPIO—These two General Purpose I/O (GPIO) pins
can individually be programmed as input or output pins.
After reset, the default state is Address Bus.
Address Bus—A8–A15 specify the address for external
Program or Data memory accesses.
Port A GPIO—These eight General Purpose I/O (GPIO) pins
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
Data Bus— D0–D15 specify the data for external program or
data memory accesses. D0–D15 are tri-stated when the external
bus is inactive. Internal pullups may be active.
Signal Description
Address, Data, and Bus Control Signals
Signal Description
Signal Description
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