DSP56F807 Motorola Inc, DSP56F807 Datasheet - Page 15

• Manufacturer Part Number: DSP56F807
• Description: 56F807 16-bit Hybrid Processor
• Manufacturer: Motorola Inc

2.13 Quad Timer Module Signals
2.14 JTAG/OnCE
Part 3 Specifications
3.1 General Characteristics
The 56F807 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such sytems, a bus may carry both 3.3V and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
56F807 Technical Data
No. of
Pins
No. of
Pins
1
1
1
1
1
1
2
4
Signal
Name
TRST
TCK
TMS
TDO
Signal
TDI
Name
TC0-1
TD0-3
DE
Table 19. JTAG/On-Chip Emulation (OnCE) Signals
(Schmitt)
(Schmitt)
(Schmitt)
(Schmitt)
Signal
Output
Output
Signal Type
Input/Output
Input/Output
Type
Input
Input
Input
Input
Freescale Semiconductor, Inc.
Table 18. Quad Timer Module Signals
For More Information On This Product,
high internally
high internally
high internally
State During
low internally
Input, pulled
Input, pulled
Input, pulled
Input, pulled
Tri-stated
Output
Reset
State During
Go to: www.freescale.com
Reset
Input
Input
Test Clock Input—This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.
Test Mode Select Input—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Test Data Input—This input pin provides a serial input data
stream to the JTAG/OnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
Test Data Output—This tri-statable output pin provides a serial
output data stream from the JTAG/OnCE port. It is driven in the
Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
Test Reset—As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete
hardware reset, TRST should be asserted at power-up and
whenever RESET is asserted. The only exception occurs in a
debugging environment when a hardware device reset is
required and it is necessary not to reset the OnCE/JTAG module.
In this case, assert RESET, but do not assert TRST.
Debug Event—DE provides a low pulse on recognized debug
events.
TC0-1—Timer C Channels 0 and 1
TD0-3—Timer D Channels 0, 1, 2, and 3
Signal Description
Signal Description
Quad Timer Module Signals
10% during
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