DSP56F807 Motorola Inc, DSP56F807 Datasheet

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DSP56F807

Manufacturer Part Number
DSP56F807
Description
56F807 16-bit Hybrid Processor
Manufacturer
Motorola Inc
Datasheet

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© Motorola, Inc., 2004. All rights reserved.
Technical Data
56F807 16-bit Hybrid Processor
3
4
3
4
4
4
4
4
4
2
4
2
4
14
4
2
2
6
6
Up to 40 MIPS at 80MHz core frequency
DSP and MCU functionality in a unified,
C-efficient architecture
Hardware DO and REP loops
MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
60K 16-bit words Program Flash
2K
8K
4K
2K
*
A/D1
A/D2
PWM Outputs
Current Sense Inputs
Fault Inputs
PWM Outputs
Current Sense Inputs
Fault Inputs
A/D1
A/D2
Quad Timer C
/Quad Timer B
Quad Timer D
includes TCS pin which is reserved for factory use and is tied to VSS
/Quad Timer
CAN 2.0A/B
Quadrature
Quadrature
Decoder 0
Dedicated
Decoder 1
/ Alt Func
GPIO
GPIO
GPIO
GPIO
SCI0
SCI1
SPI
or
or
or
VREF2
VREF
16-bit words Program RAM
16-bit words Data Flash
16-bit words Data RAM
16-bit words Boot Flash
ADCA
ADCB
tion-Specific
Peripherals
Program Memory
61440 x 16 Flash
2048 x 16 SRAM
4096 x 16 SRAM
Memory &
2048 x 16 Flash
8192 x 16 Flash
Applica-
Data Memory
Boot Flash
Watchdog
Controller
PWMA
PWMB
Interrupt
COP/
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 1. 56F807 Block Diagram
RSTO
RESET
Hardware Looping Unit
MODULE CONTROLS
ADDRESS BUS [8:0]
Program Controller
DATA BUS [15:0]
COP RESET
Go to: www.freescale.com
IRQA
and
IRQB
EXTBOOT
XAB1
XAB2
XDB2
CGDB
PDB
PAB
INTERRUPT
CONTROLS
6
JTAG/
OnCE
Port
Generation
Address
Unit
IPBus Bridge
16
VPP
(IPBB)
CONTROLS
VCAPC V
2
IPBB
Up to 64K
Program and Data memory
Two 6 channel PWM Modules
Four 4 channel, 12-bit ADCs
Two Quadrature Decoders
CAN 2.0 B Module
Two Serial Communication Interfaces (SCIs)
Serial Peripheral Interface (SPI)
Up to four General Purpose Quad Timers
JTAG/OnCE
14 Dedicated and 18 Shared GPIO lines
160-pin LQFP or 160 MAPBGA Packages
Three 16-bit Input Registers
16 x 16 + 36
Two 36-bit Accumulators
8
16
Digital Reg
DD
Data ALU
10*
16-Bit
56800
V
Low Voltage
Core
36-Bit MAC
Supervisor
SS
TM
Interface
16- bit words each of external
External
Bus
Unit
port for debugging
3
V
DDA
Analog Reg
Manipulation
Address Bus
3
Clock Gen
V
Data Bus
External
External
Control
SSA
Switch
Switch
PLL
Bus
Unit
Bit
56F807
Rev. 12.0, 02/2004
6
16
10
DSP56F807/D
A[00:05]
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
D[00:15]
PS Select
DS Select
WR Enable
RD Enable
CLKO
XTAL
EXTAL

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