DSP56F807 Motorola Inc, DSP56F807 Datasheet - Page 49

• Manufacturer Part Number: DSP56F807
• Description: 56F807 16-bit Hybrid Processor
• Manufacturer: Motorola Inc

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that
the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface
between the case of the package and the interface material. A clearance slot or hole is normally required in
the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal
performance caused by removing part of the thermal interface to the heat sink. Because of the experimental
difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate
the case temperature using a separate measurement of the thermal resistance of the interface. From this case
temperature, the junction temperature is determined from the junction-to-case thermal resistance.
5.2 Electrical Design Considerations
Use the following list of considerations to assure correct operation:
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Provide a low-impedance path from the board power supply to each V
controller, and from the board ground to each V
The minimum bypass requirement is to place 0.1 F capacitors positioned as close as possible to
the package supply pins. The recommended bypass configuration is to place one bypass capacitor
on each of the V
provide better performance tolerances.
Ensure that capacitor leads and associated printed circuit traces that connect to the chip V
V
Bypass the V
high-grade capacitor such as a tantalum capacitor.
Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be
minimal.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V
SS
pins are less than 0.5 inch per capacitor lead.
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than maximum
rated voltages to this high-impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an
appropriate voltage level.
DD
DD
and V
/V
Freescale Semiconductor, Inc.
SS
For More Information On This Product,
SS
pairs, including V
layers of the PCB with approximately 100 F, preferably with a
Go to: www.freescale.com
DD
and V
CAUTION
SS
DDA
circuits.
/V
SS
SSA.
pin.
Ceramic and tantalum capacitors tend to
DD
pin on the hybrid
56F807 Technical Data
DD
and