DSP56F807 Motorola Inc, DSP56F807 Datasheet - Page 27

• Manufacturer Part Number: DSP56F807
• Description: 56F807 16-bit Hybrid Processor
• Manufacturer: Motorola Inc

3.5.4
Operating Conditions:
3.6 External Bus Asynchronous Timing
Operating Conditions:
56F807 Technical Data
External reference crystal frequency for the PLL
PLL output frequency
PLL stabilization time
PLL stabilization time
Address Valid to WR Asserted
WR Width Asserted
Wait states = 0
Wait states > 0
WR Asserted to D0–D15 Out Valid
Data Out Hold Time from WR Deasserted
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
RD Deasserted to Address Not Valid
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
Input Data Hold to RD Deasserted
RD Assertion Width
Wait states = 0
Wait states > 0
1.
correctly. The PLL is optimized for 8MHz input crystal.2.
2.
in the User Manual. ZCLK = f
3.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
ZCLK may not exceed 80MHz. For additional information on ZCLK and f
This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
Phase Locked Loop Timing
Characteristic
Characteristic
3
3
2
Table 29. External Bus Asynchronous Timing
0
-40
V
V
o
SS
SS
to +85
o
to 0
= V
= V
Freescale Semiconductor, Inc.
op
SSA
SSA
o
o
For More Information On This Product,
C
C
= 0 V, V
= 0 V, V
Table 28. PLL Timing
Go to: www.freescale.com
DD
DD
= V
= V
1
DDA
DDA
Symbol
t
t
= 3.0–3.6 V, T
= 3.0–3.6 V, T
t
t
t
t
t
ARDD
t
WRD
AWR
DOH
DOS
RDA
DRD
t
WR
RD
Symbol
f
f
out
t
t
osc
plls
plls
/2
A
A
(T*WS) + 18.7
(T*WS)+7.5
(T*WS)+6.4
= –40 to +85 C
= –40 to +85 C, C
(T*WS)+19
Min
40
—
—
4
18.7
Min
6.5
7.5
4.8
2.2
19
—
0
0
out
External Bus Asynchronous Timing
/2, please refer to the OCCS chapter
Typ
100
—
8
1
L
1,2
50pF, f
T + 4.2
Max
—
—
—
—
—
—
—
—
—
—
—
Max
110
200
10
10
op
= 80MHz
Unit
MHz
MHz
ms
ms
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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