DSP56F807 Motorola Inc, DSP56F807 Datasheet - Page 32

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DSP56F807

Manufacturer Part Number
DSP56F807
Description
56F807 16-bit Hybrid Processor
Manufacturer
Motorola Inc
Datasheet

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Operating Conditions:
32
Clock (SCK) high time
Master
Slave
Clock (SCK) low time
Master
Slave
Data set-up time required for inputs
Master
Slave
Data hold time required for inputs
Master
Slave
Access time (time to data active from
high-impedance state)
Slave
Disable time (hold time to high-impedance state)
Slave
Data Valid for outputs
Master
Slave (after enable edge)
Data invalid
Master
Slave
Rise time
Master
Slave
Fall time
Master
Slave
1.
Parameters listed are guaranteed by design.
V
SS
= V
Freescale Semiconductor, Inc.
SSA
For More Information On This Product,
Table 31. SPI Timing
= 0 V, V
Go to: www.freescale.com
DD
= V
DDA
= 3.0–3.6 V, T
t
t
t
t
t
t
CH
DS
DH
t
t
DV
t
CL
t
DI
A
D
R
F
1
(Continued)
A
17.6
12.5
24.1
4.8
3.7
25
20
= –40 to +85 C, C
0
0
2
0
0
15.2
20.4
11.5
10.0
4.5
9.7
9.0
15
L
50pF, f
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
56F807 Technical Data
OP
Figures 21, 22,
Figures 21, 22,
Figures 21, 22,
Figures 21, 22,
Figures 21, 22,
Figures 21, 22,
Figures 21, 22,
= 80MHz
Figure
Figure
Figure
23,
23,
23,
23,
23,
23,
23,
24
24
24
24
24
24
24
24
24
24

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