MT93L04AG Zarlink Semiconductor, MT93L04AG Datasheet - Page 4

• Manufacturer Part Number: MT93L04AG
• Description: Description = 128-Channel Voice Echo CANceller ;; Package Type = Bga ;; No. Of Pins = 365
• Manufacturer: Zarlink Semiconductor

MT93L04A
Pin Description
V
V
VSS
DEVICE 1
TMS_d1
TDI_d1
TDO_d1
TCK_d1
TRSTB_d1
Test_En_d1
RESETB_d1
4
DD1
DD2
Signal Name
= 3.3V
= 1.8V
Power
Power
Power
User Signal
User Signal
User Signal
User Signal
User Signal
ICO
User
Signal
Signal Type
R6, R8, R13, R15, N15,H15,
L11,L12,L13,M8,M9,M10,M
J12,J13,K8,K9,K10,K11,K1
F15,F13,F8,F6,H6,N6, P6,
H8,H9,H10,H11,H12, H13,
R9,R10,R11,R12,M15,
L15,K15,J15,F12,F11,
F10,F9,J6, K6, L6,M6,
N9,N10,N11,N12,N13
11,M12, M13, N8,
2,K13 L8,L9,L10,
J8, J9,J10,J11,
BGA Ball #
H1
K1
K2
J4
J3
J2
J1
Positive Power Supply. Nominally 3.3 volt.
V
Positive Power Supply. Nominally 1.8 volt.
V
Ground
Test Mode Select (3.3V Input). JTAG signal that
controls the state transitions of the TAP controller.
This pin is pulled high by an internal pull-up when
not driven.
Test Serial Data In (3.3V Input). JTAG serial test
instructions and data are shifted in on this pin.
This pin is pulled high by an internal pull-up when
not driven.
Test Serial Data Out (Output). JTAG serial data
is output on this pin on the falling edge of TCK.
This pin is held in high impedance state when
JTAG scan is not enabled.
Test Clock (3.3V Input). Provides the clock to the
JTAG test logic.
Test Reset (3.3V Input). Asynchronously
initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be
pulsed low on power-up or held low, to ensure that
the MT93L00 is in the normal functional mode.
This pin is pulled by an internal pull-down when
not driven.
Internal Connection. Connected to VSS for
normal operation
Device Reset (Schmitt Trigger Input). An active
low resets the device and puts the MT93L00 into a
low-power stand-by mode.
When the RESET pin is returned to logic high
and a clock is applied to the MCLK pin, the
device will automatically execute initialization
routines, which preset all the Control and Status
Registers to their default power-up values.
DD1
DD2
= I/O Voltage
= Core Voltage
Signal Description
Preliminary Information