MT93L04AG Zarlink Semiconductor, MT93L04AG Datasheet - Page 20

• Manufacturer Part Number: MT93L04AG
• Description: Description = 128-Channel Voice Echo CANceller ;; Package Type = Bga ;; No. Of Pins = 365
• Manufacturer: Zarlink Semiconductor

MT93L04A
Pin Description (continued)
DESCRIPTION OF THE SINGLE MT93L00
Device Overview
The MT93L00 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo
cancellers, Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay
or Back-to-Back configurations. In Normal configuration, a group of echo cancellers provides two channels of
64ms echo cancellation, which run independently on different channels. In Extended Delay configuration, a
group of echo cancellers achieves 128ms of echo cancellation by cascading the two echo cancellers (A & B).
In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo
coming from both directions in a single channel, providing full-duplex 64ms echo cancellation.
Each echo canceller contains the following main elements (see Figure 3).
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Each echo canceller in the MT93L00 has four functional states: Mute, Bypass, Disable Adaptation and Enable
Adaptation. These are explained in the section entitled Echo Canceller Functional States.
Fsel_d4
Step_d4
PLLVSS1_d4
PLLVDD_d4
PLLVSS2_d4
AT1_d4
20
Halt_d4
Signal Name
Adaptive Filter for estimating the echo channel
Subtractor for cancelling the echo
Double-Talk detector for disabling the filter adaptation during periods of double-talk
Path Change detector for fast reconvergence on major echo path changes
Instability Detector to combat oscillation in very low ERL environments
Non-Linear Processor for suppression of residual echo
Disable Tone Detectors for detecting valid disable tones at send and receive path inputs
Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals
Offset Null filters for removing the DC component in PCM channels
12dB attenuator for signal attenuation
Parallel controller interface compatible with Motorola microcontrollers
PCM encoder/decoder compatible with /A-Law ITU-T G.711 or Sign-Magnitude coding
Signal
ICO
ICO
Power
Power
Power
NC
Signal Type
A11
E13
D14
E14
D15
D16
E15
BGA Ball #
Frequency select (Input). This input selects the
Master Clock frequency operation. When Fsel pin
is low, nominal 19.2MHz Master Clock input must
be applied. When Fsel pin is high, nominal
9.6MHz Master Clock input must be applied.
Internal Connection. Connected to VSS for
normal operation
Internal Connection. Connected to VSS for
normal operation
PLL Ground. Must be connected to VSS
PLL Power Supply. Must be connected to VDD2
PLL Ground. Must be connected to VSS
No connection. The pin must be left open for
normal operation.
Signal Description
Preliminary Information