MT93L04AG Zarlink Semiconductor, MT93L04AG Datasheet - Page 22

• Manufacturer Part Number: MT93L04AG
• Description: Description = 128-Channel Voice Echo CANceller ;; Package Type = Bga ;; No. Of Pins = 365
• Manufacturer: Zarlink Semiconductor

MT93L04A
Preliminary Information
In some applications the return loss can be higher or lower than 6dB. The MT93L00 allows the user to change
the detection threshold to suit each application’s need. This threshold can be set by writing the desired
threshold value into the DTDT register.
The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following
equation:
DTDT(hex) = hex(DTDT(dec) * 32768)
where 0 < DTDT(dec) < 1
Example: For DTDT = 0.5625 (-5dB), the hexadecimal value becomes
0.5625 * 32768
= 4800h
hex(
)
Path Change Detector
Integrated into the MT93L00A is a Path Change Detector. This permits fast reconvergence when a major
change occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once
convergence is achieved, but at a much slower speed.
The Path Change Detector is activated by setting the PathDet bit in Control Register A3/B3 to "1". An optional
path clearing feature can be enabled by setting the PathClr bit in Control Register A3/B3 to "1". With path
clearing turned on, the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled
with zeroes) upon detection of a major path change.
Non-Linear Processor (NLP)
After echo cancellation, there is always a small amount of residual echo which may still be audible. The
MT93L00 uses an NLP to remove residual echo signals which have a level lower than the Adaptive
Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) reference
signal as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR). TSUP can
be calculated by the following equation:
TSUP = Lrin + 20log10(NLPTHR)
where NLPTHR is the Non-Linear Processor Threshold register value
and Lrin is the relative power level expressed in dBm0.
When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual
signal by an additional 36 dB. To prevent a perceived decrease in background noise due to the activation of the
NLP, a spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This
keeps the perceived noise level constant. Consequently, the user does not hear the activation and de-activation
of the NLP.
The NLP processor can be disabled by setting the NLPDis bit to “1” in Control Register 2.
The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the following
equation:
NLPTHR(hex) = hex(NLPTHR(dec) * 32768)
where 0 < NLPTHR
< 1
(dec)
22