MT93L04AG Zarlink Semiconductor, MT93L04AG Datasheet - Page 27

• Manufacturer Part Number: MT93L04AG
• Description: Description = 128-Channel Voice Echo CANceller ;; Package Type = Bga ;; No. Of Pins = 365
• Manufacturer: Zarlink Semiconductor

Preliminary Information
MT93L04A
Enable Adaptation
In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo
canceller to model the echo return path characteristics in order to cancel echo. This is the normal operating
state.
The echo canceller functions are selected in Control Register A1/B1 and Control Register 2 through four
control bits: MuteS, MuteR, Bypass and AdaptDis. Refer to the Registers Description for details.
MT93L00 Throughput Delay
The throughput delay of the MT93L00 varies according to the device configuration. For all device
configurations, Rin to Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass
state, the Rin to Rout and Sin to Sout paths have a delay of two frames.
Serial PCM I/O channels
There are two sets of TDM I/O streams, each with channels numbered from 0 to 31. One set of input streams is
for Receive (Rin) channels, and the other set of input streams is for Send (Sin) channels. Likewise, one set of
output streams is for Rout pcm channels, and the other set is for Sout channels. See figure 6 for channel
allocation.
The arrangement and connection of PCM channels to each echo canceller is a 2 port I/O configuration for each
set of PCM Send and Receive channels, as illustrated in Figure 3.
Serial Data Interface Timing
The MT93L00 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096
MHz. The input and output data rate of the ST-Bus and GCI bus is 2.048 Mb/s.
The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The MT93L00 automatically detects the
presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second
falling edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three
quarters of the way into the bit cell (See Figure 9). In GCI format, every second rising edge of the C4i clock
marks the bit boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell
(see Figure 10).
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