MT93L04AG Zarlink Semiconductor, MT93L04AG Datasheet - Page 23

• Manufacturer Part Number: MT93L04AG
• Description: Description = 128-Channel Voice Echo CANceller ;; Package Type = Bga ;; No. Of Pins = 365
• Manufacturer: Zarlink Semiconductor

Preliminary Information
The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register A1/B1. It should
be noted that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled.
If the comfort noise injector is unable to correctly match the level of the background noise (because of peculiar
spectral characteristics, for example), the injected level can be fine-tuned using the Noise Scaling register. A
neutral value of 80(hex) will prevent any scaling. Values less than 80(hex) will reduce the noise level, values
greater than 80(hex) will increase the noise level. The scaling is done linearly.
Example: To decrease the comfort noise level by 3 dB, the register value would be 10 ^ (-3 / 20) • 128 = 0.71 •
128 = 91(dec) = 5B(hex)
The default factory setting for the Noise Scaling register should be adequate for most operating environments.
It is unlikely that it will need to be changed. It has also been set to a value which will ensure G.168 compliance.
Disable Tone Detector
G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz
( 21Hz) sine wave, a power level between -6 to -31dBm0, and a phase reversal of 180 degrees ( 25 degrees)
every 450ms ( 25ms). If the disable tone is present for a minimum of one second with at least one phase
reversal, the Tone Detector will trigger.
G.164 recommendation defines the disable tone as a 2100 Hz ( 21Hz) sine wave with a power level between 0
to -31dBm0. If the disable tone is present for a minimum of 400 milliseconds, with or without phase reversal,
the Tone Detector will trigger.
The MT93L00 has two Tone Detectors per channels (for a total of 64) in order to monitor the occurrence of a
valid disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will
indicate logic high and an interrupt is generated (i.e. IRQ pin low). Refer to Figure 4 and to the Interrupts
section.
Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165)
to maintain Tone Detector status (i.e. TD bit high). The Tone Detector status will only release (i.e. TD bit low) if
the signals Rin and Sin fall below -30dBm0, in the frequency range of 390Hz to 700Hz, and below -34dBm0,
in the frequency range of 700Hz to 3400Hz, for at least 400ms. Whenever a Tone Detector releases, an
interrupt is generated (i.e. IRQ pin low).
The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a
per channel basis. When the PHDis bit is set to 1, G.164 tone disable requirements are selected.
In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to
the Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone
Detectors internally control the switching between Enable Adaptation and Bypass states. The automatic mode
Rin
Sin
Rin
Sin
Figure 4 - Disable Tone Detection
Tone Detector
Tone Detector
Tone Detector
Tone Detector
Echo Canceller A
Echo Canceller B
Status reg
Status reg
TD
TD bit
ECA
ECB
bit
MT93L04A
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