MT93L04AG Zarlink Semiconductor, MT93L04AG Datasheet - Page 28

• Manufacturer Part Number: MT93L04AG
• Description: Description = 128-Channel Voice Echo CANceller ;; Package Type = Bga ;; No. Of Pins = 365
• Manufacturer: Zarlink Semiconductor

MT93L04A
Memory Mapped Control and Status registers
Internal memory and registers are memory mapped into the address space of the HOST interface. The internal
dual ported memory is mapped into segments on a “per channel” basis to monitor and control each individual
echo canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes
use of Echo Canceller B from group 2. It occupies the internal address space from 0A0h to 0BFh and interfaces
to PCM channel #5 on all serial PCM I/O streams.
As illustrated in Figure 7, the “per channel” registers provide independent control and status bits for each echo
canceller. Figure 8 shows the memory map of the control/status register blocks for all echo cancellers.
When Extended Delay or Back-to-Back configuration is selected, Control Register A1/B1 and Control Register
2 of the selected group of echo cancellers require special care. Refer to the Register description section.
Table 2 is a list of the channels used for the 16 groups of echo cancellers when they are configured as
Extended Delay or Back-to-Back
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Figure 7 - Memory Mapping of per channel Control and Status Registers
Base
Addr +
00h Control Reg A1
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
Control Reg 2
Status Reg
Reserved
Flat Delay Reg
Reserved
Decay Step Size Reg
Decay Step Number
Control Reg A3
Control Reg A4
Noise Scaling
Injection Rate
Rin Peak Detect Reg
Sin Peak Detect Reg
Error Peak Detect Reg
Reserved
DTDT Reg
Reserved
NLPTHR
Step Size, MU
Reserved
Reserved
Echo Canceller A
Base
Addr +
20h Control Reg B1
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
Control Reg 2
Status Reg
Reserved
Flat Delay Reg
Reserved
Decay Step Size Reg
Decay Step Number
Control Reg B3
Control Reg B4
Noise Scaling
Injection Rate
Rin Peak Detect Reg
Sin Peak Detect Reg
Error Peak Detect Reg
Reserved
DTDT Reg
Reserved
NLPTHR
Step Size, MU
Reserved
Reserved
Echo Canceller B
Preliminary Information