MT57V1MH18E Micron Semiconductor Products, Inc., MT57V1MH18E Datasheet - Page 3

• Manufacturer Part Number: MT57V1MH18E
• Description: 18Mb DDR SRAM, 2.5V Vdd, Hstl, 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Programmable Impedance Output
Buffer
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V
resistor must be five times the desired impedance. For
example, a 350 W resistor is required for an output
impedance of 70 W . To ensure that output impedance is
one-fifth the value of RQ (within 15 percent), the range
of RQ is 175 W to 350 W . Alternately, the ZQ ball can be
connected directly to V
device in a minimum impedance mode.
because variations may occur in supply voltage and
temperature over time. The device samples the value
of RQ. An update
the system. Impedance updates do not affect device
operation, and all data sheet timing and current speci-
fications are met during an update.
set at 50 W . To guarantee optimum output driver
impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.
18Mb: 2.5V V
MT57V1MH18E_16_F.fm – Rev. F, Pub. 3/03
The DDR SRAM is equipped with programmable
Output impedance updates may be required
The device will power up with an output impedance
DD
, HSTL, Pipelined DDRb4 SRAM
o
f the impedance is transparent to
DD
Q, which will place the
SS
. The value of the
2.5V V
3
DD
Clocking
approaches. C and C# may be supplied to the SRAM to
synchronize data output across multiple devices,
enabling the bus master to receive all data simulta-
neously. If C and C# are not provided (tied HIGH) K
and K# are used as the output timing reference.
alternative for data synchronization. The echo clocks
are controlled exactly like the DQ signals except that
CQ and CQ# have an additional small delay for easier
data capture by the bus master. Echo clocks must be
separately received for each SRAM in the system. Use
of echo clocks maximizes the available data window
for each SRAM in the system.
output data. CQ and CQ# are both rising edge and fall-
ing edge accurate and are 180° out of phase. Either or
both may be used for output data capture. K or C rising
edge triggers CQ rising and CQ# falling edge. CQ rising
edge indicates first data response for QDRI and DDRI
(version 1, non-DLL) SRAM, while CQ# rising edge
indicates first data response for QDRII and DDRII (ver-
sion 2, DLL) SRAM.
, HSTL, PIPELINED DDRb4 SRAM
The
The echo clocks (CQ and CQ#) provide another
The output echo clocks are precise references to
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR
SRAM
1 MEG x 18, 512K x 36
supports
flexible
©2003 Micron Technology, Inc.
clocking