MT57V1MH18E Micron Semiconductor Products, Inc., MT57V1MH18E Datasheet - Page 14

• Manufacturer Part Number: MT57V1MH18E
• Description: 18Mb DDR SRAM, 2.5V Vdd, Hstl, 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Notes
18Mb: 2.5V V
MT57V1MH18E_16_F.fm – Rev. F, Pub. 3/03
1. Outputs
2. Outputs are impedance-controlled. I
3. All voltages referenced to V
4. Overshoot:
5. AC load current is higher than the shown DC val-
6. HSTL outputs meet JEDEC HSTL Class I and Class
7. The nominal value of V
8. To maintain a valid level, the transitioning edge of
9. I
(V
2)/(RQ/5) for values of 175 W £ RQ £ 350 W .
Undershoot: V
Power-up:
and V
During normal operation, V
V
widths less than
rates less than
ues. AC I/O curves are available upon request.
II standards.
range of 1.5V to 1.8V DC, and the variation of
V
the input must:
a. Sustain a constant slew rate from the current AC
b. Reach at least the target AC level
c. After the AC target level is reached, continue to
increases with faster cycle times. I
with faster cycle times and greater output loading.
Typical value is measured at 6ns cycle time.
DD
DD
DD
maintain at least the target DC level, V
V
DD
DD
level through the target AC level, V
V
IH
, HSTL, Pipelined DDRb4 SRAM
IH
. Control input signals may not have pulse
Q must be limited to ±0.1V DC.
is specified with no output current and
Q/2)/(RQ/5) for values of 175 W £ RQ £ 350 W .
(
DD
(
DC
AC
Q £ 1.4V for t £ 200ms
)
)
are
V
V
IH
t
IH
IL
KHKH (MIN).
impedance-controlled.
(
(
t
AC
£ V
AC
KHKL (MIN) or operate at cycle
) ³ -0.5V for t £
) £ V
DD
DD
Q + 0.3V and V
DD
Q may be set within the
SS
+ 0.7V for t £
DD
(GND).
Q must not exceed
t
DD
KHKH/2
OL
Q increases
DD
= (V
t
IL
KHKH/2
IL
|I
(
OH
(
2.5V V
£ 2.4V
AC
DC
DD
|
) or
) or
Q/
=
14
DD
10. Typical values are measured at V
11. NOP currents are valid when entering NOP after
12. Average I/O current and power is provided for
13. This parameter is sampled.
14. Average thermal resistance between the die and
15. Junction temperature is a function of total device
16. Control input signals may not be operated with
17. Test conditions as specified with the output load-
18. If C and C# are tied HIGH, then K, K# become the
19.
20. This is a synchronous device. All addresses, data,
, HSTL, PIPELINED DDRb4 SRAM
1.5V, and temperature = 25°C.
all pending READ and WRITE cycles are com-
pleted.
informational purposes only and is not tested.
Calculation assumes that all outputs are loaded
with C
of outputs toggle at each transition (for example,
n = 18 for x36), C
equations: Average I/O Power as dissipated by the
SRAM is:
P = 0.5 × n x f x V
n x f x V
the case top surface per MIL SPEC 883 Method
1012.1.
power dissipation and device mounting environ-
ment. Measured per SEMI G38-87.
pulse widths less than
ing as shown in Figure 5, unless otherwise noted.
references for C and C# timing parameters.
t
and temperature.
and control lines must meet the specified setup
and hold times for all latching clock edges.
CHQXI is greater than
Micron Technology, Inc., reserves the right to change products or specifications without notice.
L
DD
(in farads), f = input clock frequency, half
Q x (C
1 MEG x 18, 512K x 36
DD
L
O
+ C
= 6pF, V
Q
2
O
x (C
t
).
t
KHKL (MIN).
CHQZ at any given voltage
L
DD
+ 2C
Q = 1.5V and uses the
O
DD
). Average I
©2003 Micron Technology, Inc.
=2.5V, V
DD
DD
Q =
Q =