ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet - Page 48

• Manufacturer Part Number: ADZS-BF537-EZLITE
• Description: Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Analog Devices

ADSP-BF534/ADSP-BF536/ADSP-BF537
10/100 Ethernet MAC Controller Timing
Table 40
describe the 10/100 Ethernet MAC controller operations. This
feature is only available on the ADSP-BF536 and ADSP-BF537
processors.
Table 40. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
1
Table 41. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
1
Table 42. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
1
Table 43. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
1
Parameter
f
t
t
t
Parameter
f
t
t
t
Parameter
f
t
t
t
Parameter
t
t
MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
MII outputs synchronous to ETxCLK are ETxD3–0.
RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
RMII outputs synchronous to RMII REF_CLK are ETxD1–0.
ERXCLK
ERXCLKW
ERXCLKIS
ERXCLKIH
ETXCLK
ETXCLKW
ETXCLKOV
ETXCLKOH
REFCLK
REFCLKW
REFCLKIS
REFCLKIH
REFCLKOV
REFCLKOH
through
1
1
1
1
ERxCLK Frequency (f
ERxCLK Width (t
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)
ETxCLK Frequency (f
ETxCLK Width (t
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)
ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold)
REF_CLK Frequency (f
REF_CLK Width (t
Rx Input Valid to RMII REF_CLK Rising Edge (Data In Setup)
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In Hold)
Table 45
RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid)
RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold)
and
Figure 30
ERxCLK
ETXCLK
REFCLK
SCLK
SCLK
= ERxCLK Period)
= ETxCLK Period)
SCLK
= REFCLK Period)
= SCLK Frequency)
= SCLK Frequency)
through
= SCLK Frequency)
Figure 35
Rev. I | Page 48 of 68 | July 2010
Min
None
t
7.5
7.5
Min
None
t
0
Min
None
t
4
2
ERxCLK
ETxCLK
REFCLK
× 35%
× 35%
× 35%
Min
2
Max
25 + 1%
f
t
Max
25 + 1%
f
t
20
Max
50 + 1%
2 × f
t
SCLK
SCLK
ERxCLK
ETxCLK
REFCLK
+ 1%
+ 1%
SCLK
× 65%
× 65%
× 65%
+ 1%
Max
7.5
Unit
MHz
Unit
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns