ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet - Page 31

• Manufacturer Part Number: ADZS-BF537-EZLITE
• Description: Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Analog Devices

TIMING SPECIFICATIONS
Component specifications are subject to change
without notice.
Clock and Reset Timing
Table 22. Clock Input and Reset Timing
1
2
3
4
5
Table 23. Power-Up Reset Timing
Parameter
Timing Requirements
t
Parameter
Timing Requirements
t
t
t
t
t
t
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
Applies to PLL bypass mode and PLL non bypass mode.
CLKIN frequency must not change on the fly.
If the DF bit in the PLL_CTL register is set, then the maximum t
Applies when processor is configured in No Boot Mode (BMODE2-0 = b#000).
RST_IN_PWR
CKIN
CKINL
CKINH
BUFDLAY
WRST
NOBOOT
by default the PLL is multiplying the CLKIN frequency by 10, 300 MHz and 400 MHz speed grade parts can not use the full CLKIN period range.
V
DD_SUPPLIES
RESET
CLKIN
RESET Deasserted After the V
Within Specification
CLKBUF
RESET
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
CLKIN to CLKBUF Delay
RESET Asserted Pulse Width Low
RESET Deassertion to First External Access Delay
CLKIN
1, 2, 3, 4
t
CKINL
t
CKIN
DDINT
t
CKINH
, V
In
DDEXT
Figure
, V
CKIN
t
Rev. I | Page 31 of 68 | July 2010
RST_IN_PWR
DDRTC
Figure 10. Power-Up Reset Timing
Figure 9. Clock and Reset Timing
period is 50 ns.
10, V
t
WRST
, and CLKIN Pins Are Stable and
DD_SUPPLIES
5
is V
DDINT
ADSP-BF534/ADSP-BF536/ADSP-BF537
, V
VCO
DDEXT
, f
t
NOBOOT
CCLK
, V
t
DDRTC
, and f
BUFDLAY
Min
3500 × t
SCLK
settings discussed in
CKIN
Min
20.0
8.0
8.0
11 × t
3 × t
CKIN
CKIN
Table 10
Max
t
BUFDLAY
Max
100.0
10
5 × t
through
CKIN
Table
14. Since
Unit
ns
Unit
ns
ns
ns
ns
ns
ns