ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet - Page 39

• Manufacturer Part Number: ADZS-BF537-EZLITE
• Description: Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Analog Devices

Serial Port Timing
Table 30
through
Table 30. Serial Ports—External Clock
1
2
3
Table 31. Serial Ports—Internal Clock
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Referenced to sample edge.
Verified in design but untested. After being enabled, the serial port requires external clock pulses—before the first external frame sync edge—to initialize the serial port.
Referenced to drive edge.
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
Applies to all nonautomotive-grade devices when operated within either of these voltage ranges.
Applies to all nonautomotive-grade devices when operated within these voltage ranges.
All automotive-grade devices are within these specifications.
Referenced to sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
SCLKEW
SCLKE
SUDTE
SUDRE
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
DFSI
HOFSI
DDTI
HDTI
SCLKIW
Figure 23 on Page 42
through
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
TSCLKx/RSCLKx Width
Table 33 on Page 42
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
TSCLKx/RSCLKx Width
TSCLKx/RSCLKx Period
Start-Up Delay From SPORT Enable To First External TFSx
Start-Up Delay From SPORT Enable To First External RFSx
TFSx/RFSx Delay After TSCLKx/RSCLK (Internally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLK (Internally Generated TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
5
5
describe serial port operations.
and
Figure 20 on Page 40
4
5
5
4
4
2
4
2
Rev. I | Page 39 of 68 | July 2010
1
1
1
Min
8.5
–1.5
8.5
–1.5
4.5
ADSP-BF534/ADSP-BF536/ADSP-BF537
1.0
1.0
2
0.80 V V
2
2.25 V V
DDINT
DDEXT
or
Max
3.0
3.0
2
3
< 0.95 V
< 2.70 V
1
Min
8.0
–1.5
8.0
–1.5
4.5
1.0
1.0
Min
3.0
3.0
3.0
4.5
15.0
4.0 × t
4.0 × t
0
0
0.95 V V
2.70 V V
SCLKE
SCLKE
DDINT
and
DDEXT
Max
3.0
3.0
Max
10.0
10.0
1.43 V
3.60 V
2, 3
Unit
ns
ns
ns
4.5
15.0
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns