ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet - Page 20

• Manufacturer Part Number: ADZS-BF537-EZLITE
• Description: Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Analog Devices

ADSP-BF534/ADSP-BF536/ADSP-BF537
PIN DESCRIPTIONS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pin
definitions are listed in
functionality and reduce package size and pin count, some pins
have dual, multiplexed functions. In cases where pin function is
reconfigurable, the default state is shown in plain text, while the
alternate function is shown in italics. Pins shown with an aster-
isk after their name (*) offer high source/high sink current
capabilities.
All pins are three-stated during and immediately after reset,
with the exception of the external memory interface, asynchro-
nous and synchronous memory control, and the buffered XTAL
output pin (CLKBUF). On the external memory interface, the
Table 9. Pin Descriptions
Pin Name
Memory Interface
Asynchronous Memory Control
Synchronous Memory Control
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
BR
BG
BGH
AMS3–0
ARDY
AOE
ARE
AWE
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
Table
9. In order to maintain maximum
Type Function
O
I/O
O
I
O
O
O
I
O
O
O
O
O
O
O
O
O
O
Address Bus for Async Access
Data Bus for Async/Sync Access
Byte Enables/Data Masks for Async/Sync Access
Bus Request (This pin should be pulled high when not used.)
Bus Grant
Bus Grant Hang
Bank Select (Require pull-ups if hibernate is used.)
Hardware Ready Control
Output Enable
Read Enable
Write Enable
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable(Requires a pull-down if hibernate with SDRAM self-refresh is
used.)
Clock Output
A10 Pin
Bank Select
Rev. I | Page 20 of 68 | July 2010
control and address lines are driven high, with the exception of
CLKOUT, which toggles at the system clock rate. If BR is active
(whether or not RESET is asserted), the memory pins are also
three-stated. During hibernate, all outputs are three-stated
unless otherwise noted in
All I/O pins have their input buffers disabled with the exception
of the pins noted in the data sheet that need pull-ups or pull-
downs if unused.
The SDA (serial data) and SCL (serial clock) pins are open drain
and therefore require a pull-up resistor. Consult version 2.1 of
the I
2
C specification for the proper resistor value.
Table
9.
Driver
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
1