ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet - Page 25

• Manufacturer Part Number: ADZS-BF537-EZLITE
• Description: Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Analog Devices

Table 10
requirements for the ADSP-BF534/ADSP-BF536/ADSP-BF537
processor clocks. Take care in selecting MSEL, SSEL, and CSEL
Table 10. Core Clock Requirements—500 MHz, 533 MHz, and 600 MHz Speed Grades
1
2
3
Table 11. Core Clock Requirements—400 MHz Speed Grade
1
2
Table 12. Core Clock Requirements—300 MHz Speed Grade
1
Table 13. Phase-Locked Loop Operating Conditions
Table 14. System Clock Requirements
1
2
Parameter
f
f
f
f
f
f
f
See
Applies to 600 MHz models only. See
Applies to 533 MHz and 600 MHz models only. See
Parameter
f
f
f
f
f
See
See
Parameter
f
f
f
f
f
See
Parameter
f
Parameter
f
f
f
Rounded number. Actual test specification is SCLK period of 7.5 ns. See
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
VCO
SCLK
SCLK
SCLK
Ordering Guide on Page
Ordering Guide on Page
Operating Conditions on Page
Ordering Guide on Page
1
1
must be less than or equal to f
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
through
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Table 12
Voltage Controlled Oscillator (VCO) Frequency
68.
68.
68.
describe the voltage/frequency
CCLK
24.
Ordering Guide on Page
and is subject to additional restrictions for SDRAM interface operation. See
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
Condition
V
V
DDEXT
DDEXT
=1.045 V Minimum) 1.10 V
=1.14 V Minimum) 1.20 V
= 0.95 V Minimum) 1.00 V
= 0.85 V Minimum) 0.90 V
= 0.8 V Minimum) 0.85 V
=1.30 V Minimum)
= 1.20 V Minimum)
=1.14 V Minimum)
=1.045 V Minimum)
= 0.95 V Minimum)
= 0.85 V Minimum)
= 0.8 V Minimum)
=1.14 V Minimum)
=1.045 V Minimum)
= 0.95 V Minimum)
= 0.85 V Minimum)
= 0.8 V Minimum)
Ordering Guide on Page
3.3 V or 2.5 V, V
3.3 V or 2.5 V, V
68.
Rev. I | Page 25 of 68 | July 2010
Internal Regulator Setting Max
2
DDINT
DDINT
3
Table 27 on Page
68.
1
1
1.14 V
1.14 V
Internal Regulator Setting
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
Internal Regulator Setting
1.30 V
1.25 V
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
35.
ratios so as not to exceed the maximum core clock and system
clock.
conditions.
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 13
400
333
295
describes phase-locked loop operating
1
120°C T
Table 27 on Page
Max
133
100
Min
50
J
2
105°C
Max
600
533
500
444
400
333
250
35.
Max
300
255
210
180
160
Max
Max f
Max
400
363
333
280
250
All
CCLK
2
Other T
J
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
Unit
MHz
Unit
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
MHz
MHz
MHz