ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet - Page 47

• Manufacturer Part Number: ADZS-BF537-EZLITE
• Description: Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Analog Devices

JTAG Test and Emulation Port Timing
Table 39
Table 39. JTAG Port Timing
1
2
3
Parameter
Timing Parameters
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs = DATA15–0, BR, ARDY, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH15–0, MDIO, TCK, TRST, RESET, NMI, RTXI,
50 MHz maximum
System Outputs = DATA15–0, ADDR19–1, ABE1–0, BG, BGH, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, MDC, MDIO,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
BMODE2–0.
TSCLK0, TFS0, RFS0, RSCLK0, DT0PRI, DT0SEC, PF15–0, PG15–0, PH15–0, RTXO, TDO, EMU, XTAL, VROUT1–0.
and
OUTPUTS
SYSTEM
SYSTEM
INPUTS
TCK
TMS
TDO
Figure 29
TDI
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width
TDO Delay From TCK Low
System Outputs Delay After TCK Low
describe JTAG port operations.
2
(Measured in TCK Cycles)
t
DSYS
t
DTDO
t
TCK
t
SSYS
t
Rev. I | Page 47 of 68 | July 2010
STAP
1
3
1
Figure 29. JTAG Port Timing
t
HTAP
t
HSYS
ADSP-BF534/ADSP-BF536/ADSP-BF537
Min
20
4
4
4
5
4
0
Max
10
12
Unit
ns
ns
ns
ns
ns
TCK
ns
ns