ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet - Page 16

• Manufacturer Part Number: ADZS-BF537-EZLITE
• Description: Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Analog Devices

ADSP-BF534/ADSP-BF536/ADSP-BF537
ence signal in other timing specifications as well. While active
by default, it can be disabled using the EBIU_SDGCTL and
EBIU_AMGCTL registers.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
Table 6. Example System Clock Ratios
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of f
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table
fast core frequency modifications.
Table 7. Core Clock Ratios
The maximum CCLK frequency not only depends on the part’s
speed grade (see
the applied V
on Page 25
depends on the chip package and the applied V
Table 14 on Page
BOOTING MODES
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor has six
mechanisms (listed in
nal and external memory after a reset. A seventh mode is
provided to execute from external memory, bypassing the boot
sequence.
Signal Name
SSEL3–0
0001
0110
1010
Signal Name
CSEL1–0
00
01
10
11
Table 6
7. This programmable core clock capability is useful for
illustrates typical system clock ratios.
for details). The maximal system clock rate (SCLK)
DDINT
Ordering Guide on Page
Divider Ratio
VCO:SCLK
1:1
6:1
10:1
Divider Ratio
VCO:CCLK
1:1
2:1
4:1
8:1
25).
voltage (see
Table
8) for automatically loading inter-
Table
VCO
100
300
500
VCO
300
300
500
200
Example Frequency Ratios
Example Frequency Ratios
SCLK
10,
. The SSEL value can be
Table
68), it also depends on
(MHz)
(MHz)
DDEXT
11, and
SCLK
100
50
50
CCLK
300
150
125
25
voltage (see
Rev. I | Page 16 of 68 | July 2010
Table 12
Table 8. Booting Modes
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:
BMODE2–0
000
001
010
011
100
101
110
111
• Execute from 16-bit external memory – Execution starts
• Boot from 8-bit and 16-bit external flash memory – The
• Boot from serial SPI memory (EEPROM or flash) – 8-, 16-,
• Boot from SPI host device – The Blackfin processor oper-
• Boot from UART – Using an autobaud handshake
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
8-bit or 16-bit flash boot routine located in Boot ROM
memory space is set up using asynchronous memory
bank 0. All configuration settings are set for the slowest
device possible (3-cycle hold time; 15-cycle R/W access
times; 4-cycle setup). The Boot ROM evaluates the first
byte of the boot stream at address 0x2000 0000. If it is 0x40,
8-bit boot is performed. A 0x60 byte assumes a 16-bit
memory device and performs 8-bit DMA. A 0x20 byte also
assumes 16-bit memory but performs 16-bit DMA.
or 24-bit addressable devices are supported as well as
AT45DB041, AT45DB081, AT45DB161, AT45DB321,
AT45DB642, and AT45DB1282 DataFlash
Atmel. The SPI uses the PF10/SPI SSEL1 output pin to
select a single SPI EEPROM/flash device, submits a read
command and successive address bytes (0x00) until a valid
8-, 16-, or 24-bit, or Atmel addressable device is detected,
and begins clocking data into the processor.
ates in SPI slave mode and is configured to receive the bytes
of the .LDR file from an SPI host (master) agent. To hold
off the host device from transmitting while the boot ROM
is busy, the Blackfin processor asserts a GPIO pin, called
host wait (HWAIT), to signal the host device not to send
any more bytes until the flag is deasserted. The flag is cho-
sen by the user and this information is transferred to the
Blackfin processor via bits 10:5 of the FLAG header.
sequence, a boot-stream-formatted program is downloaded
by the host. The host agent selects a baud rate within the
UART’s clocking capabilities. When performing the auto-
baud, the UART expects an “@” (boot stream) character
Description
Execute from 16-bit external memory (bypass
boot ROM)
Boot from 8-bit or 16-bit memory
(EPROM/flash)
Reserved
Boot from serial SPI memory (EEPROM/flash)
Boot from SPI host (slave mode)
Boot from serial TWI memory (EEPROM/flash)
Boot from TWI host (slave mode)
Boot from UART host (slave mode)
®
devices from