ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet - Page 15

• Manufacturer Part Number: ADZS-BF537-EZLITE
• Description: Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Analog Devices

Figure 5
complete the power management system. The regulator con-
trols the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the
processor core while keeping I/O power supplied. While in
hibernate state, V
for external buffers. The voltage regulator can be activated from
this power-down state by asserting the RESET pin, which then
initiates a boot sequence. The regulator can also be disabled and
bypassed at the user’s discretion. For additional information on
voltage regulation, see Switching Regulator Design Consider-
ations for the ADSP-BF533 Blackfin Processors (EE-228).
CLOCK SIGNALS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors can
be clocked by an external crystal, a sine wave input, or a buff-
ered, shaped clock derived from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the processors include an on-chip oscilla-
tor circuit, an external crystal can be used. For fundamental
frequency operation, use the circuit shown in
parallel-resonant, fundamental frequency, microprocessor-
grade crystal is connected across the CLKIN and XTAL pins.
The on-chip resistance between CLKIN and the XTAL pin is in
the 500 k range. Further parallel resistors are typically not rec-
ommended. The two capacitors and the series resistor shown in
Figure 6
The capacitor and resistor values shown in
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations of multiple
devices over temperature range.
A third-overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in
ation is discussed in detail in the application note Using Third
Overtone Crystals with the ADSP-218x DSP (EE-168).
The CLKBUF pin is an output pin, and is a buffer version of the
input clock. This pin is particularly useful in Ethernet applica-
tions to limit the number of required clock sources in the
system. In this type of application, a single 25 MHz or 50 MHz
crystal can be applied directly to the processors. The 25 MHz or
50 MHz output of CLKBUF can then be connected to an exter-
nal Ethernet MII or RMII PHY device.
Because of the default 10× PLL multiplier, providing a 50 MHz
CLKIN exceeds the recommended operating conditions of the
lower speed grades. Because of this restriction, an RMII PHY
shows the typical external components required to
fine-tune phase and amplitude of the sine frequency.
Figure
6. A design procedure for third-overtone oper-
DDEXT
can still be applied, eliminating the need
Figure 6
Figure
are typical
6. A
Rev. I | Page 15 of 68 | July 2010
requiring a 50 MHz clock input cannot be clocked directly from
the CLKBUF pin for the lower speed grades. In this case, either
provide a separate 50 MHz clock source, or use an RMII PHY
with 25 MHz clock input options. The CLKBUF output is active
by default and can be disabled using the VR_CTL register for
power savings.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable 0.5× to 64× multiplication
factor (bounded by specified minimum and maximum VCO
frequencies). The default multiplier is 10×, but it can be modi-
fied by a software instruction sequence in the PLL_CTL register.
On-the-fly CCLK and SCLK frequency changes can be effected
by simply writing to the PLL_DIV register. Whereas the maxi-
mum allowed CCLK and SCLK rates depend on the applied
voltages V
up to the frequency specified by the part’s speed grade. The
CLKOUT pin reflects the SCLK frequency to the off-chip world.
It belongs to the SDRAM interface, but it functions as a refer-
ADSP-BF534/ADSP-BF536/ADSP-BF537
CLKIN
CLKOUT
CLKBUF
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY.
REQUIRES PLL SEQUENCING
DDINT
“FINE” ADJUSTMENT
0.5u to 64u
Figure 7. Frequency Modification Methods
PLL
and V
EN
Figure 6. External Crystal Connections
EN
DDEXT
CLKIN
18 pF *
BLACKFIN
Figure
, the VCO is always permitted to run
SCLK d 133 MHz
SCLK d CCLK
VCO
330
TO PLL CIRCUITRY
7, the core clock (CCLK) and
*
“COARSE” ADJUSTMENT
350
XTAL
18 pF *
÷ 1 to 15
÷ 1, 2, 4, 8
1M
ON-THE-FLY
OPERATION ONLY:
V
FOR OVERTONE
DDEXT
CCLK
SCLK