ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet - Page 17

• Manufacturer Part Number: ADZS-BF537-EZLITE
• Description: Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Analog Devices

For each of the boot modes, a 10-byte header is first brought in
from an external device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks can be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
To augment the boot modes, a secondary software loader can be
added to provide additional booting mechanisms. This second-
ary loader could provide the capability to boot from flash,
variable baud rate, and other sources. In all boot modes except
bypass, program execution starts from on-chip L1 memory
address 0xFFA0 0000.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the
programmer to use many of the processor core resources in a
single instruction. Coupled with many features more often seen
on microcontrollers, this instruction set is very efficient when
compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.
• Boot from serial TWI memory (EEPROM/flash) – The
• Boot from TWI host – The TWI host agent selects the slave
(8 bits data, 1 start bit, 1 stop bit, no parity bit) on the RXD
pin to determine the bit rate. It then replies with an
acknowledgement that is composed of 4 bytes: 0xBF, the
value of UART_DLL, the value of UART_DLH, and 0x00.
The host can then download the boot stream. When the
processor needs to hold off the host, it deasserts CTS.
Therefore, the host must monitor this signal.
Blackfin processor operates in master mode and selects the
TWI slave with the unique ID 0xA0. It submits successive
read commands to the memory device starting at 2-byte
internal address 0x0000 and begins clocking data into the
processor. The TWI memory device should comply with
Philips I
bility to auto-increment its internal address counter such
that the contents of the memory device can be read
sequentially.
with the unique ID 0x5F. The processor replies with an
acknowledgement and the host can then download the
boot stream. The TWI host agent should comply with
Philips I
plexer can be used to select one processor at a time when
booting multiple processors from a single TWI.
2
2
C Bus Specification version 2.1 and have the capa-
C Bus Specification version 2.1. An I
2
C multi-
Rev. I | Page 17 of 68 | July 2010
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
DEVELOPMENT TOOLS
Blackfin processors are supported with a complete set of
CROSSCORE
including Analog Devices emulators and the VisualDSP++
development environment. The same emulator hardware that
supports other Analog Devices processors also fully emulates
the Blackfin processor family.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler that is based on an algebraic
syntax, an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ runtime library that includes DSP and mathemati-
cal functions. A key point for these tools is C/C++ code
efficiency. The compiler has been developed for efficient
translation of C/C++ code to Blackfin assembly. The Blackfin
processor has architectural features that improve the efficiency
of compiled C/C++ code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and
†
‡
ADSP-BF534/ADSP-BF536/ADSP-BF537
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
• Seamlessly integrated DSP/MCU features are optimized for
• A multi-issue load/store modified-Harvard architecture,
• All registers, I/O, and memory are mapped into a unified
• Microcontroller features, such as arbitrary bit and bit-field
• Code density enhancements, which include intermixing of
both 8-bit and 16-bit operations.
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
4G byte memory space, providing a simplified program-
ming model.
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
®†
software and hardware development tools,
®‡