DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 658

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

19.7
To eliminate noise from the subclock input to OSCI, the subclock is sampled using the dividing
clock φ. The sampling frequency is set using the NESEL bit of LPWRCR. For details, see section
19.1.2, Low Power Control Register (LPWRCR).
No sampling is performed in subactive mode, subsleep mode, or watch mode.
19.8
The PLL circuit has the function of doubling or tripling the 16-MHz or 24-MHz clock from the
main oscillator to generate the 48-MHz USB operating clock.
When the PLL circuit is used, set the UCKS3 to UCKS0 bits of UCTLR. For details, refer to
section 14, Universal Serial Bus (USB).
When the PLL circuit is not used, connect the PLVCC pin to Vcc and the PLLVSS pin to the
ground (Vss). Figure 19.9 shows examples of external circuits peripheral to the PLL.
Rev.7.00 Dec. 24, 2008 Page 604 of 698
REJ09B0074-0700
16-MHz or
24-MHz
crystal
resonator
or external
clock
Subclock Waveform Generation Circuit
PLL Circuit for USB
Note: * CB, CPB is laminated ceramic.
EXTAL
XTAL
PLLVSS
PLLVCC
VCC
VSS
(1) PLL is used
Figure 19.9 Example of PLL Circuit
CB: 0.1μF*
R
P
: 200Ω
CPB: 0.1μF*
Vcc
6- to 24-MHz
crystal
resonator
or external
clock
EXTAL
XTAL
(2) PLL is not used
PLLVCC
PLLVSS
VCC
VSS
Vcc