DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 179
DF2211NP24V
Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
1.DF2211NP24V.pdf
(756 pages)
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6.3.5
BCRL performs selection of the external bus-released state protocol, and enabling or disabling of
WAIT pin input.
The functions selected by this register are available only in the H8S/2218 Group. This register
should not be modified in the H8S/2212 Group.
Note: * These bits should be set to 0 in the H8S/2212 Group.
Bit
7
6
5
4
3
2, 1 –
0
Bit Name
BRLE*
–
–
–
–
WAITE*
Bus Control Register L (BCRL)
Initial Value R/W
0
0
0
0
1
All 0
0
R/W
R/W
–
R/W
R/W
R/W
R/W
Description
Bus Release Enable
Enables or disables external bus release.
0: External bus release is disabled. BREQ and BACK
1: External bus release is enabled.
Reserved
The write value should always be 0.
Reserved
This bit is always read as 0 and cannot be modified.
Reserved
The write value should always be 0.
Reserved
The write value should always be 1.
Reserved
The write value should always be 0.
WAIT Pin Enable
Selects enabling or disabling of wait input by the WAIT
pin.
0: Wait input by WAIT pin disabled. WAIT pin can be
1: Wait input by WAIT pin enabled.
used as I/O port.
can be used as I/O ports.
Rev.7.00 Dec. 24, 2008 Page 125 of 698
REJ09B0074-0700
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