DSPIC33FJ64GP306 Microchip Technology Inc., DSPIC33FJ64GP306 Datasheet - Page 81

• Manufacturer Part Number: DSPIC33FJ64GP306
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

6.0
The dsPIC33FJXXXGPX06/X08/X10 interrupt control-
ler reduces the numerous peripheral interrupt request
signals to a single interrupt request signal to the
dsPIC33FJXXXGPX06/X08/X10 CPU. It has the fol-
lowing features:
• Up to 8 processor exceptions and software traps
• 7 user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
• Fixed interrupt entry and return latencies
6.1
The Interrupt Vector Table is shown in Figure 6-1. The
IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
8 nonmaskable trap vectors plus up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this priority is linked to their position in the
vector table. All other things being equal, lower
addresses have a higher natural priority. For example,
the interrupt associated with vector 0 will take priority
over interrupts at any other vector address.
dsPIC33FJXXXGPX06/X08/X10 devices implement up
to 67 unique interrupts and 5 nonmaskable traps.
These are summarized in Table 6-1 and Table 6-2.
© 2007 Microchip Technology Inc.
Note:
source
support
INTERRUPT CONTROLLER
Interrupt Vector Table
This data sheet summarizes the features
of this group of dsPIC33FJXXXGPX06/
X08/X10 devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to the “dsPIC33F Family Reference
Manual”. Please refer to the Microchip
web site (www.microchip.com) for the lat-
est dsPIC33F Family Reference Manual
sections.
dsPIC33FJXXXGPX06/X08/X10
6.1.1
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 6-1. Access to the
AIVT
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a means to
switch between an application and a support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
6.2
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33FJXXXGPX06/X08/X10 device clears its
registers in response to a Reset, which forces the PC
to zero. The digital signal controller then begins pro-
gram execution at location 0x000000. The user pro-
grams a GOTO instruction at the Reset address which
redirects program execution to the appropriate start-up
routine.
Note:
is
Reset Sequence
provided
ALTERNATE VECTOR TABLE
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
by
the
ALTIVT
DS70286A-page 79
control
bit