DSPIC33FJ64GP306 Microchip Technology Inc., DSPIC33FJ64GP306 Datasheet - Page 79

• Manufacturer Part Number: DSPIC33FJ64GP306
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

TABLE 5-3:
5.2.1
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
© 2007 Microchip Technology Inc.
POR
BOR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
crystal oscillator is used).
Reset Type
2:
3:
4:
5:
6:
T
T
Power-up Timer delay (if regulator is disabled). T
states, including waking from Sleep mode, only if the regulator is enabled.
T
T
oscillator clock to the system.
T
T
POR AND LONG OSCILLATOR
START-UP TIMES
STARTUP
OST
RST
POR
LOCK
FSCM
= Internal state Reset time (20 μs nominal).
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
= Power-on Reset delay (10 μs nominal).
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
= PLL lock time (20 μs nominal).
= Fail-Safe Clock Monitor delay (100 μs nominal).
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
Any Clock
Any Clock
Any Clock
Any Clock
Any Clock
= Conditional POR delay of 20 μs nominal (if on-chip regulator is enabled) or 64 ms nominal
Clock Source
dsPIC33FJXXXGPX06/X08/X10
T
T
T
T
POR
POR
POR
POR
T
T
T
T
SYSRST Delay
STARTUP
STARTUP
STARTUP
STARTUP
+ T
+ T
+ T
+ T
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
STARTUP
RST
RST
RST
RST
+ T
+ T
+ T
+ T
5.2.2
If the FSCM is enabled, it begins to monitor the system
clock source when SYSRST is released. If a valid clock
source is not available at this time, the device auto-
matically switches to the FRC oscillator and the user
can switch to the desired crystal oscillator in the Trap
Service Routine.
5.2.2.1
When the system clock source is provided by a crystal
oscillator and/or the PLL, a small delay, T
matically inserted after the POR and PWRT delay
times. The FSCM does not begin to monitor the system
clock source until this delay expires. The FSCM delay
time is nominally 500 μs and provides additional time
for the oscillator and/or PLL to stabilize. In most cases,
the FSCM delay prevents an oscillator failure trap at a
device Reset when the PWRT is disabled.
RST
RST
RST
RST
is also applied to all returns from powered-down
System Clock
T
T
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
OST
OST
FSCM Delay for Crystal and PLL
Clock Sources
T
T
Delay
T
T
LOCK
LOCK
OST
+ T
OST
+ T
—
—
—
—
—
—
—
—
LOCK
LOCK
FSCM
T
T
T
T
T
T
Delay
FSCM
FSCM
FSCM
FSCM
FSCM
FSCM
—
—
—
—
—
—
—
—
DS70286A-page 77
1, 2, 3
1, 2, 3, 5, 6
1, 2, 3, 4, 6
1, 2, 3, 4, 5, 6
3
3, 5, 6
3, 4, 6
3, 4, 5, 6
3
3
3
3
3
3
FSCM
Notes
, is auto-