DSPIC33FJ64GP306 Microchip Technology Inc., DSPIC33FJ64GP306 Datasheet - Page 127

• Manufacturer Part Number: DSPIC33FJ64GP306
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

7.0
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer),
and buffers or variables stored in RAM, with minimal
CPU
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
The dsPIC33FJXXXGPX06/X08/X10 peripherals that
can utilize DMA are listed in Table 7-1 along with their
associated Interrupt Request (IRQ) numbers.
TABLE 7-1:
© 2007 Microchip Technology Inc.
INT0
Input Capture 1
Input Capture 2
Output Compare 1
Output Compare 2
Timer2
Timer3
SPI1
SPI2
UART1 Reception
UART1 Transmission
UART2 Reception
UART2 Transmission
ADC1
ADC2
DCI
ECAN1 Reception
Note:
intervention.
DIRECT MEMORY ACCESS
(DMA)
This data sheet summarizes the features
of
of dsPIC33FJXXXGPX06/X08/X10
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “dsPIC33F Family Reference Manual”
. Please refer to the Microchip web site
(www.microchip.com)
dsPIC33F
sections.
Peripheral
PERIPHERALS WITH DMA
SUPPORT
The
Family
this
DMA
Reference
for
dsPIC33FJXXXGPX06/X08/X10
IRQ Number
controller
the
10
33
12
30
31
13
21
60
34
11
0
1
5
2
6
7
8
Manual
group
latest
can
The DMA controller features eight identical data
transfer channels.
Each channel has its own set of control and status
registers. Each DMA channel can be configured to
copy data either from buffers stored in dual port DMA
RAM to peripheral SFRs, or from peripheral SFRs to
buffers in DMA RAM.
The DMA controller supports the following features:
• Word or byte sized data transfers.
• Transfers from peripheral to DMA RAM or DMA
• Indirect Addressing of DMA RAM locations with or
• Peripheral Indirect Addressing – In some
• One-Shot Block Transfers – Terminating DMA
• Continuous Block Transfers – Reloading DMA
• Ping-Pong Mode – Switching between two DMA
• Automatic or manual initiation of block transfers
• Each channel can select from 20 possible
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.
ECAN1 Transmission
ECAN2 Reception
ECAN2 Transmission
RAM to peripheral.
without automatic post-increment.
peripherals, the DMA RAM read/write addresses
may be partially derived from the peripheral.
transfer after one block transfer.
RAM buffer start address after every block
transfer is complete.
RAM start addresses between successive block
transfers, thereby filling two buffers alternately.
sources of data sources or destinations.
Peripheral
DS70286A-page 125
IRQ Number
70
55
71