DSPIC33FJ64GP306 Microchip Technology Inc., DSPIC33FJ64GP306 Datasheet - Page 145

• Manufacturer Part Number: DSPIC33FJ64GP306
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

9.0
The dsPIC33FJXXXGPX06/X08/X10 devices provide
the ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower con-
sumed
devices can manage power consumption in four differ-
ent ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
9.1
dsPIC33FJXXXGPX06/X08/X10 devices allow a wide
range of clock frequencies to be selected under appli-
cation control. If the system clock configuration is not
locked, users can choose low-power or high-precision
oscillators by simply changing the NOSC bits (OSC-
CON<10:8>). The process of changing a system clock
during operation, as well as limitations to the process,
are discussed in more detail in Section 8.0 “Oscillator
Configuration”.
9.2
dsPIC33FJXXXGPX06/X08/X10 devices have two
special power-saving modes that are entered through
the execution of a special PWRSAV instruction. Sleep
EXAMPLE 9-1:
© 2007 Microchip Technology Inc.
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
Note:
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
Instruction-Based Power-Saving
Modes
power.
This data sheet summarizes the features
of
of dsPIC33FJXXXGPX06/X08/X10
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “dsPIC33F Family Reference Manual”.
Please refer to the Microchip web site
(www.microchip.com)
dsPIC33F
sections.
dsPIC33FJXXXGPX06/X08/X10
PWRSAV INSTRUCTION SYNTAX
Family
; Put the device into SLEEP mode
; Put the device into IDLE mode
this
Reference
for
dsPIC33FJXXXGPX06/X08/X10
the
Manual
group
latest
mode stops clock operation and halts all code execu-
tion. Idle mode halts the CPU and code execution, but
allows peripheral modules to continue operation. The
assembly syntax of the PWRSAV instruction is shown in
Example 9-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to “wake-up”.
9.2.1
Sleep mode has these features:
• The system clock source is shut down. If an
• The device current consumption is reduced to a
• The Fail-Safe Clock Monitor does not operate
• The LPRC clock continues to run in Sleep mode if
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals may continue
The device will wake-up from Sleep mode on any of the
these events:
• Any interrupt source that is individually enabled.
• Any form of device Reset.
• A WDT time-out.
On wake-up from Sleep, the processor restarts with the
same clock source that was active when Sleep mode
was entered.
on-chip oscillator is used, it is turned off.
minimum, provided that no I/O pin is sourcing
current.
during Sleep mode since the system clock source
is disabled.
the WDT is enabled.
prior to entering Sleep mode.
to operate in Sleep mode. This includes items such
as the input change notification on the I/O ports, or
peripherals that use an external clock input. Any
peripheral that requires the system clock source for
its operation is disabled in Sleep mode.
Note:
SLEEP MODE
SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
DS70286A-page 143