DSPIC33FJ64GP306 Microchip Technology Inc., DSPIC33FJ64GP306 Datasheet - Page 159

• Manufacturer Part Number: DSPIC33FJ64GP306
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

14.0
14.1
When the OCM control bits (OCxCON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OCx pin to the low state and generates a single
output pulse.
To generate a single output pulse, the following steps
are required (these steps assume timer source is
initially turned off but this is not a requirement for the
module operation):
1. Determine the instruction clock cycle time. Take
2. Calculate time to the rising edge of the output pulse
3. Calculate the time to the falling edge of the pulse
4. Write the values computed in steps 2 and 3 above
5. Set Timer Period register, PRy, to value equal to or
6. Set the OCM bits to ‘100’ and the OCTSEL
7. Set the TON (TyCON<15>) bit to ‘1’, which enables
8. Upon the first match between TMRy and OCxR, the
9. When the incrementing timer, TMRy, matches the
10. To initiate another single pulse output, change the
© 2007 Microchip Technology Inc.
Note:
into account the frequency of the external clock to
the timer source (if one is used) and the timer
prescaler settings.
relative to the TMRy start value (0000h).
based on the desired pulse width and the time to the
rising edge of the pulse.
into the Output Compare register, OCxR, and the
Output Compare Secondary register, OCxRS,
respectively.
greater than value in OCxRS, the Output Compare
Secondary register.
(OCxCON<3>) bit to the desired timer source. The
OCx pin state will now be driven low.
the compare time base to count.
OCx pin will be driven high.
Output Compare Secondary register, OCxRS, the
second and trailing edge (high-to-low) of the pulse
is driven onto the OCx pin. No additional pulses are
driven onto the OCx pin and it remains at low. As a
result of the second compare match event, the
OCxIF interrupt flag bit is set, which will result in an
interrupt if it is enabled, by setting the OCxIE bit. For
further information on peripheral interrupts, refer to
Section 6.0 “Interrupt Controller”.
Timer and Compare register settings, if needed,
and then issue a write to set the OCM bits to ‘100’.
OUTPUT COMPARE
Setup for Single Output Pulse
Generation
This data sheet summarizes the features
of this group of dsPIC33FJXXXGPX06/
X08/X10 devices. It is not intended to be a
comprehensive reference source.
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual” . Please refer to the
Microchip web site (www.microchip.com)
for the latest dsPIC33F Family Reference
Manual sections.
dsPIC33FJXXXGPX06/X08/X10
To
The output compare module does not have to be dis-
abled after the falling edge of the output pulse. Another
pulse can be initiated by rewriting the value of the
OCxCON register.
14.2
When the OCM control bits (OCxCON<2:0>) are set to
‘101’, the selected output compare channel initializes
the OCx pin to the low state and generates output
pulses on each and every compare match event.
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required (these steps assume timer source is
initially turned off but this is not a requirement for the
module operation):
1. Determine the instruction clock cycle time. Take
2. Calculate time to the rising edge of the output pulse
3. Calculate the time to the falling edge of the pulse,
4. Write the values computed in step 2 and 3 above
5. Set Timer Period register, PRy, to a value equal to
6. Set the OCM bits to ‘101’ and the OCTSEL bit to the
7. Enable the compare time base by setting the TON
8. Upon the first match between TMRy and OCxR, the
9. When the compare time base, TMRy, matches the
10. As a result of the second compare match event, the
11. When the compare time base and the value in its
12. Steps 8 through 11 are repeated and a continuous
Disabling and re-enabling of the timer, and clearing
the TMRy register, are not required but may be
advantageous for defining a pulse from a known
event time boundary.
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
relative to the TMRy start value (0000h).
based on the desired pulse width and the time to the
rising edge of the pulse.
into the Output Compare register, OCxR, and the
Output Compare Secondary register, OCxRS,
respectively.
or greater than value in OCxRS, the Output
Compare Secondary register.
desired timer source. The OCx pin state will now be
driven low.
(TyCON<15>) bit to ‘1’.
OCx pin will be driven high.
Output Compare Secondary register, OCxRS, the
second and trailing edge (high-to-low) of the pulse
is driven onto the OCx pin.
OCxIF interrupt flag bit is set.
respective Timer Period register match, the TMRy
register resets to 0x0000 and resumes counting.
stream of pulses is generated, indefinitely. The
OCxIF flag is set on each OCxRS-TMRy compare
match event.
Setup for Continuous Output
Pulse Generation
DS70286A-page 157