DSPIC33FJ64GP306 Microchip Technology Inc., DSPIC33FJ64GP306 Datasheet - Page 25

• Manufacturer Part Number: DSPIC33FJ64GP306
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

2.5
The dsPIC33FJXXXGPX06/X08/X10 ALU is 16 bits
wide and is capable of addition, subtraction, bit shifts
and logic operations. Unless otherwise mentioned,
arithmetic operations are 2’s complement in nature.
Depending on the operation, the ALU may affect the
values of the Carry (C), Zero (Z), Negative (N), Over-
flow (OV) and Digit Carry (DC) Status bits in the SR
register. The C and DC Status bits operate as Borrow
and Digit Borrow bits, respectively, for subtraction oper-
ations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W reg-
ister array, or data memory, depending on the address-
ing mode of the instruction. Likewise, output data from
the ALU can be written to the W register array or a data
memory location.
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.
The dsPIC33FJXXXGPX06/X08/X10 CPU incorpo-
rates hardware support for both multiplication and divi-
sion. This includes a dedicated hardware multiplier and
support hardware for 16-bit-divisor division.
2.5.1
Using the high-speed 17-bit x 17-bit multiplier of the DSP
engine, the ALU supports unsigned, signed or mixed-sign
operation in several MCU multiplication modes:
1.
2.
3.
4.
5.
6.
7.
2.5.2
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1.
2.
3.
4.
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide algo-
rithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
© 2007 Microchip Technology Inc.
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
Arithmetic Logic Unit (ALU)
MULTIPLIER
DIVIDER
dsPIC33FJXXXGPX06/X08/X10
2.6
The DSP engine consists of a high-speed, 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
The dsPIC33FJXXXGPX06/X08/X10 is a single-cycle,
instruction flow architecture; therefore, concurrent opera-
tion of the DSP engine with MCU instruction flow is not
possible. However, some MCU ALU and DSP engine
resources may be used concurrently by the same instruc-
tion (e.g., ED, EDAC).
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations which
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Control register
(CORCON), as listed below:
1.
2.
3.
4.
5.
6.
7.
Table 2-1 provides a summary of DSP instructions. A
block diagram of the DSP engine is shown in
Figure 2-3.
TABLE 2-1:
CLR
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY
MPY.N
MSC
Instruction
Fractional or integer DSP multiply (IF).
Signed or unsigned DSP multiply (US).
Conventional or convergent rounding (RND).
Automatic saturation on/off for AccA (SATA).
Automatic saturation on/off for AccB (SATB).
Automatic saturation on/off for writes to data
memory (SATDW).
Accumulator Saturation mode selection (ACCSAT).
DSP Engine
DSP INSTRUCTIONS
SUMMARY
A = 0
A = (x – y)
A = A + (x – y)
A = A + (x * y)
A = A + x
No change in A
A = x * y
A = x
A = – x * y
A = A – x * y
Operation
Algebraic
2
2
2
2
DS70286A-page 23
ACC Write
Back
Yes
Yes
Yes
Yes
No
No
No
No
No
No