DSPIC33FJ64GP306 Microchip Technology Inc., DSPIC33FJ64GP306 Datasheet - Page 181

• Manufacturer Part Number: DSPIC33FJ64GP306
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

17.0
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules avail-
able in the dsPIC33FJXXXGPX06/X08/X10 device
family. The UART is a full-duplex asynchronous system
that can communicate with peripheral devices, such as
personal computers, LIN, RS-232 and RS-485 inter-
faces. The module also supports a hardware flow con-
trol option with the UxCTS and UxRTS pins and also
includes an IrDA
The primary features of the UART module are:
• Full-Duplex, 8 or 9-bit Data Transmission through
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
FIGURE 17-1:
© 2007 Microchip Technology Inc.
Note:
the UxTX and UxRX pins
Note 1: Both UART1 and UART2 can trigger a DMA data transfer. If U1TX, U1RX, U2TX or U2RX is selected as
2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e.,
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
This data sheet summarizes the features
of this group of dsPIC33FJXXXGPX06/
X08/X10 devices. It is not intended to be a
comprehensive reference source.
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual” . Please refer to the
Microchip web site (www.microchip.com)
for the latest dsPIC33F Family Reference
Manual sections.
a DMA IRQ source, a DMA transfer occurs when the U1TXIF, U1RXIF, U2TXIF or U2RXIF bit gets set as
a result of a UART1 or UART2 transmission or reception.
UTXISEL<1:0> = 00 and URXISEL<1:0> = 00).
®
encoder and decoder.
UART SIMPLIFIED BLOCK DIAGRAM
Hardware Flow Control
Baud Rate Generator
UART Transmitter
UART Receiver
dsPIC33FJXXXGPX06/X08/X10
IrDA
®
To
• Hardware Flow Control Option with UxCTS and
• Fully Integrated Baud Rate Generator with 16-bit
• Baud Rates Ranging from 1 Mbps to 15 bps at
• 4-deep First-In-First-Out (FIFO) Transmit Data
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-bit mode with Address Detect
• Transmit and Receive Interrupts
• A Separate Interrupt for all UART Error Conditions
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA Support
A simplified block diagram of the UART is shown in
Figure 17-1. The UART module consists of the key
important hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
UxRTS pins
Prescaler
16 MIPS
Buffer
(9th bit = 1)
UxRTS
UxCTS
UxRX
UxTX
BCLK
DS70286A-page 179