DSPIC33FJ64GP306 Microchip Technology Inc., DSPIC33FJ64GP306 Datasheet - Page 247

• Manufacturer Part Number: DSPIC33FJ64GP306
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

21.0
dsPIC33FJXXXGPX06/X08/X10 devices include sev-
eral features intended to maximize application flexibility
and reliability, and minimize cost through elimination of
external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
TABLE 21-1:
© 2007 Microchip Technology Inc.
0xF80000 FBS
0xF80002 FSS
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E RESERVED3
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Note 1:
Address
Note:
2:
SPECIAL FEATURES
These reserved bits read as ‘1’ and must be programmed as ‘1’.
Unimplemented bits are read as ‘0’.
This data sheet summarizes the features
of
of dsPIC33FJXXXGPX06/X08/X10
devices. It is not intended to be a
comprehensive reference source.
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual” . Please refer to the
Microchip web site (www.microchip.com)
for the latest dsPIC33F Family Reference
Manual sections.
Name
DEVICE CONFIGURATION REGISTER MAP
FWDTEN
this
IESO
Bit 7
FCKSM<1:0>
—
—
RBS<1:0>
RSS<1:0>
dsPIC33FJXXXGPX06/X08/X10
WINDIS
Bit 6
—
—
—
group
To
Bit 5
—
—
—
—
—
—
—
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
21.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The device Configuration register map is shown in
Table 21-1.
The individual Configuration bit descriptions for the
FBS, FSS, FGS, FOSCSEL, FOSC, FWDT, FPOR and
FICD Configuration registers are shown in Table 21-2.
Note that address 0xF80000 is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (0x800000-0xFFFFFF) which can only be
accessed using table reads and table writes.
The upper byte of all device Configuration registers
should always be ‘1111
appear to be NOP instructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘1’s to these locations
has no effect on device operation.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
WDTPRE
Bit 4
Reserved
—
—
—
—
—
—
Configuration Bits
(1)
Bit 3
—
—
—
—
BSS<2:0>
SSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
GSS1
Bit 2
1111’. This makes them
FNOSC<2:0>
FPWRT<2:0>
DS70286A-page 245
GSS0
Bit 1
GWRP
BWRP
SWRP
Bit 0