DSPIC33FJ64GP306 Microchip Technology Inc., DSPIC33FJ64GP306 Datasheet
DSPIC33FJ64GP306
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DSPIC33FJ64GP306 Summary of contents
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... Microchip Technology Inc. Data Sheet High-Performance, 16-Bit Digital Signal Controllers DS70286A ...
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... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified logo, microID, MPLAB, PIC DSCs code hopping ® ® © 2007 Microchip Technology Inc. ...
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... available interrupt sources • external interrupts • 7 programmable priority levels • 5 processor exceptions © 2007 Microchip Technology Inc. dsPIC33FJXXXGPX06/X08/X10 Digital I/O: • programmable digital I/O pins • Wake-up/Interrupt-on-Change pins • Output pins can drive from 3.0V to 3.6V • ...
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... Industrial temperature • Low-power consumption Packaging: • 100-pin TQFP (14x14x1 mm and 12x12x1 mm) • 80-pin TQFP (12x12x1 mm) • 64-pin TQFP (10x10x1 mm) Note: See the device variant tables for exact peripheral features per device. © 2007 Microchip Technology Inc. ...
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... MCU embedded applications. The variants with codec interfaces are well-suited for speech and audio processing applications. dsPIC33F General Purpose Family Variants Program Flash Device Pins Memory (Kbyte) (Kbyte) dsPIC33FJ64GP206 64 64 dsPIC33FJ64GP306 64 64 dsPIC33FJ64GP310 100 64 dsPIC33FJ64GP706 64 64 dsPIC33FJ64GP708 80 64 dsPIC33FJ64GP710 100 64 ...
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... AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70286A-page dsPIC33FJ64GP206 41 40 dsPIC33FJ128GP206 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2007 Microchip Technology Inc. ...
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... AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2007 Microchip Technology Inc dsPIC33FJ64GP306 41 dsPIC33FJ128GP306 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 ...
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... AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70286A-page dsPIC33FJ256GP506 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2007 Microchip Technology Inc. ...
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... SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2007 Microchip Technology Inc dsPIC33FJ64GP706 41 dsPIC33FJ128GP706 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 ...
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... AN2/SS1/CN4/RB2 18 PGC3/EMUC3/AN1/CN3/RB1 19 PGD3/EMUD3/AN0/CN2/RB0 20 DS70286A-page dsPIC33FJ64GP708 51 dsPIC33FJ128GP708 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 SDA2/INT4/RA3 SCL2/INT3/RA2 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 © 2007 Microchip Technology Inc. ...
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... SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 20 AN5/CN7/RB5 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2007 Microchip Technology Inc. dsPIC33FJ64GP310 dsPIC33FJ128GP310 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 71 IC4/RD11 IC3/RD10 70 69 IC2/RD9 IC1/RD8 68 INT4/RA15 67 INT3/RA14 OSC2/CLKO/RC15 63 OSC1/CLKIN/RC12 V 62 ...
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... PGD3/EMUD3/AN0/CN2/RB0 DS70286A-page 10 dsPIC33FJ256GP510 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 71 IC3/RD10 70 69 IC2/RD9 IC1/RD8 68 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 64 OSC1/CLKIN/RC12 TDO/RA5 TDI/RA4 60 SDA2/RA3 59 58 SCL2/RA2 57 SCL1/RG2 SDA1/RG3 56 SCK1/INT0/RF6 55 54 SDI1/RF7 SDO1/RF8 53 U1RX/RF2 52 51 U1TX/RF3 © 2007 Microchip Technology Inc. ...
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... SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2007 Microchip Technology Inc. dsPIC33FJ64GP710 dsPIC33FJ128GP710 dsPIC33FJ256GP710 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 72 71 IC4/RD11 70 IC3/RD10 IC2/RD9 69 68 IC1/RD8 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 63 OSC1/CLKIN/RC12 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70286A-page 12 © 2007 Microchip Technology Inc. ...
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... Reference Manual”. Please refer to the Microchip web site (www.microchip.com) for the latest dsPIC33F Family Reference Manual sections. This document contains device specific information for the following devices: • dsPIC33FJ64GP206 • dsPIC33FJ64GP306 • dsPIC33FJ64GP310 • dsPIC33FJ64GP706 • dsPIC33FJ64GP708 • dsPIC33FJ64GP710 • dsPIC33FJ128GP206 • dsPIC33FJ128GP306 • ...
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... EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support 16-bit ALU MCLR OC/ DCI ADC1,2 PWM1-8 CN1-23 SPI1,2 I2C1,2 PORTA DMA RAM PORTB DMA 16 Controller PORTC PORTD 16 PORTE 16 16 PORTF 16 PORTG ECAN1,2 UART1,2 © 2007 Microchip Technology Inc. ...
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... I/O ST Legend: CMOS = CMOS compatible input or output; Analog = Analog input ST = Schmitt Trigger input with CMOS levels Output Input Power © 2007 Microchip Technology Inc. Description Analog input channels. Positive supply for analog modules. Ground reference for analog modules. External clock source input. Always associated with OSC1 pin function. ...
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... UART2 clear to send. UART2 ready to send. UART2 receive. UART2 transmit. Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. © 2007 Microchip Technology Inc. ...
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... X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and © 2007 Microchip Technology Inc. Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific ...
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... X RAM Y RAM Address Address Loop Latch Control Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support DMA 16 RAM DMA Controller 16-bit ALU 16 To Peripheral Modules © 2007 Microchip Technology Inc. ...
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... Accumulators AccB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH © 2007 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 ...
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... Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70286A-page 20 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2007 Microchip Technology Inc. ...
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... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). © 2007 Microchip Technology Inc. (2) DS70286A-page 21 ...
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... This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70286A-page 22 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2007 Microchip Technology Inc. ...
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... The divide algo- rithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. © 2007 Microchip Technology Inc. 2.6 DSP Engine The DSP engine consists of a high-speed, 17-bit x ...
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... FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70286A-page 24 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2007 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter prior to accumulation. © 2007 Microchip Technology Inc. 2.6.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true, or complement data into the other input ...
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... Section 2.6.2.4 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. © 2007 Microchip Technology Inc. (see ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2007 Microchip Technology Inc. 2.6.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70286A-page 28 © 2007 Microchip Technology Inc. ...
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... The dsPIC33FJXXXGPX06/X08/X10 architecture fea- tures separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution. © 2007 Microchip Technology Inc. 3.1 Program Address Space The program dsPIC33FJXXXGPX06/X08/X10 devices is 4M instruc- group tions ...
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... Reserved Reserved Device Configuration Device Configuration Registers Registers Reserved Reserved DEVID (2) DEVID (2) 0x000000 Instruction 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 0x00ABFE 0x00AC00 0x0157FE 0x015800 0x02ABFE 0x02AC00 0x7FFFFE 0x800000 0xF7FFFE 0xF80000 0xF80017 0xF80010 0xFEFFFE 0xFF0000 0xFFFFFE © 2007 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (read as ‘0’) © 2007 Microchip Technology Inc. 3.1.2 INTERRUPT AND TRAP VECTORS All dsPIC33FJXXXGPX06/X08/X10 devices reserve the addresses between 0x00000 and 0x000200 for organized in hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code ...
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... Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field using Indirect Addressing mode using a working register as an Address Pointer. These are used by the © 2007 Microchip Technology Inc. ...
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... Kbyte 0x17FF 0x1801 SRAM Space 0x1FFF 0x2001 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2007 Microchip Technology Inc. LSb 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 ...
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... Program Memory 0xFFFF DS70286A-page 34 LSb Address 16 bits MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x1FFE 0x27FE 0x2800 Y Data RAM (Y) 0x3FFE 0x4000 DMA RAM 0x47FE 0x4800 0x8000 X Data Unimplemented (X) 0xFFFE 8 Kbyte Near Data Space © 2007 Microchip Technology Inc. ...
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... SFR Space 0x07FF 0x0801 30-Kbyte 0x47FF SRAM Space 0x4801 0x77FF 0x7800 0x7FFF 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2007 Microchip Technology Inc. LSb Address 16 bits MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x47FE 0x4800 Y Data RAM (Y) 0x77FE 0x7800 ...
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... DMA RAM location. Therefore, the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU. Note: DMA RAM can be used for general purpose data storage if the DMA function is not required in an application. © 2007 Microchip Technology Inc. ...
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TABLE 3-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — — — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CNPU2 ...
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TABLE 3-3: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF AD1IF U1TXIF IFS1 0086 ...
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TABLE 3-4: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 3-5: INPUT CAPTURE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ...
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TABLE 3-6: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...
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TABLE 3-7: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — I2C1TRN 0202 — — — I2C1BRG 0204 — — — I2C1CON 0206 I2CEN — I2CSIDL SCLREL I2C1STAT 0208 ...
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TABLE 3-9: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...
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TABLE 3-13: ADC1 REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 AD1CON1 0320 ADON — ADSIDL ADDMABM AD1CON2 0322 VCFG<2:0> — AD1CON3 0324 ADRC — — AD1CHS123 0326 — — — — AD1CHS0 ...
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TABLE 3-15: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...
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TABLE 3-15: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5CNT 03C6 — — — — DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE — — — DMA6STA 03CC DMA6STB 03CE DMA6PAD ...
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TABLE 3-16: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — C1VEC 0404 — — — C1FCTRL 0406 ...
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TABLE 3-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 SID<10:3> C1RXM0EID 0432 EID<15:8> ...
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TABLE 3-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11SID 046C SID<10:3> C1RXF11EID 046E EID<15:8> C1RXF12SID 0470 SID<10:3> C1RXF12EID 0472 EID<15:8> C1RXF13SID 0474 SID<10:3> C1RXF13EID 0476 EID<15:8> C1RXF14SID ...
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TABLE 3-19: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = File Name Addr Bit 15 Bit 14 Bit 13 C2CTRL1 0500 — — CSIDL C2CTRL2 0502 — — — C2VEC 0504 — — — C2FCTRL 0506 DMABS<2:0> C2FIFO 0508 ...
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TABLE 3-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0500 - 051E C2BUFPNT1 0520 F3BP<3:0> C2BUFPNT2 0522 F7BP<3:0> C2BUFPNT3 0524 F11BP<3:0> C2BUFPNT4 0526 F15BP<3:0> C2RXM0SID 0530 SID<10:3> C2RXM0EID 0532 ...
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TABLE 3-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C2RXF10EID 056A EID<15:8> C2RXF11SID 056C SID<10:3 C2RXF11EID 056E EID<15:8> C2RXF12SID 0570 SID<10:3 C2RXF12EID 0572 EID<15:8> C2RXF13SID 0574 SID<10:3 C2RXF13EID ...
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TABLE 3-22: DCI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name DCICON1 0280 DCIEN — DCISIDL — DCICON2 0282 — — — — DCICON3 0284 — — — — DCISTAT 0286 — — — — ...
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TABLE 3-25: PORTC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISC 02CC TRISC15 TRISC14 TRISC13 TRISC12 PORTC 02CE RC15 RC14 RC13 RC12 LATC 02D0 LATC15 LATC14 LATC13 LATC12 Legend unknown value ...
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TABLE 3-29: PORTG REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISG 02E4 TRISG15 TRISG14 TRISG13 TRISG12 PORTG 02E6 RG15 RG14 RG13 RG12 LATG 02E8 LATG15 LATG14 LATG13 LATG12 ODCG 06E4 ODCG15 ODCG14 ODCG13 ...
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... PC<22:16> 000000000 <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2007 Microchip Technology Inc. 3.2.8 DATA RAM PROTECTION FEATURE The dsPIC33F product family supports Data RAM protection features which enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled ...
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... Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing © 2007 Microchip Technology Inc. ...
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... Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2007 Microchip Technology Inc. The length of a circular buffer is not directly specified determined by corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes) ...
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... BREN (XBREV<15>) bit, then a write to using the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. N bytes, should not be enabled disabled. However, Modulo © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address ...
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... D<15:0> refers to a data space word. Program Space Address <23> <22:16> <15> PC<22:1> 0 0xx xxxx xxxx xxxx TBLPAG<7:0> 0xxx xxxx xxxx xxxx xxxx xxxx TBLPAG<7:0> 1xxx xxxx xxxx xxxx xxxx xxxx PSVPAG<7:0> xxxx xxxx © 2007 Microchip Technology Inc. <14:1> <0> 0 xxxx xxx0 Data EA<15:0> Data EA<15:0> (1) Data EA<14:0> xxx xxxx xxxx xxxx ...
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... Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2007 Microchip Technology Inc. Program Counter 0 23 bits ...
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... TBLRDH.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in 0x800000 the user memory area © 2007 Microchip Technology Inc. ...
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... PSVPAG is mapped into the upper half of the data memory space... © 2007 Microchip Technology Inc. 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...
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... NOTES: DS70286A-page 66 © 2007 Microchip Technology Inc. ...
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... Using 1/0 Table Instruction User/Configuration Space Select © 2007 Microchip Technology Inc. just before shipping the product. This also allows the most recent firmware or a custom firmware to be pro- grammed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user can write program memory data either in blocks or ‘ ...
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... Flash in RTSP mode. A programming operation is nominally duration and the processor stalls (waits) until the oper- ation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. required for © 2007 Microchip Technology Inc. ...
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... No operation 1011 = Reserved 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2007 Microchip Technology Inc. (1) U-0 U-0 — — (1) U-0 R/W-0 R/W-0 — ...
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... Bit is set bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (Write Only) bits DS70286A-page 70 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...
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... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2007 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted © 2007 Microchip Technology Inc. ...
Page 75
... Internal Regulator V DD Trap Conflict Illegal Opcode Uninitialized W Register © 2007 Microchip Technology Inc. Note: Refer to the specific peripheral or CPU section of this manual for register Reset states. group All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1). A POR will clear all bits, except for the POR bit (RCON< ...
Page 76
... If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70286A-page 74 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) U-0 R/W-0 — — VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 77
... All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2007 Microchip Technology Inc. (1) (CONTINUED) DS70286A-page 75 ...
Page 78
... SYSRST delay times. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released. Clearing Event POR POR POR POR PWRSAV instruction, POR POR POR — — © 2007 Microchip Technology Inc. ...
Page 79
... The device will not begin to execute code until a valid clock source has been released to the system. There- fore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known. © 2007 Microchip Technology Inc. System Clock SYSRST Delay Delay ...
Page 80
... Reset value for the Reset Control register, RCON, depends on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, depends on the type of Reset and the programmed values of the oscillator Configuration bits in the FOSC Configuration register. DS70286A-page 78 © 2007 Microchip Technology Inc. ...
Page 81
... These are summarized in Table 6-1 and Table 6-2. © 2007 Microchip Technology Inc. 6.1.1 ALTERNATE VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the ...
Page 82
... Note 1: See Table 6-1 for the list of implemented interrupt vectors. DS70286A-page 80 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 (1) (1) © 2007 Microchip Technology Inc. ...
Page 83
... Microchip Technology Inc. AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C DMA0 – DMA Channel 0 0x00011E IC2 – ...
Page 84
... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error DMA Error Trap Reserved Reserved © 2007 Microchip Technology Inc. ...
Page 85
... The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2007 Microchip Technology Inc. The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...
Page 86
... Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) R/W-0 R/W-0 US EDT R/W-0 R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set © 2007 Microchip Technology Inc. ...
Page 87
... DMACERR: DMA Controller Error Status bit 1 = DMA controller error trap has occurred 0 = DMA controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...
Page 88
... STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70286A-page 86 © 2007 Microchip Technology Inc. ...
Page 89
... Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 R/W-0 ...
Page 90
... T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70286A-page 88 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF R/W-0 R/W-0 R/W-0 DMA01IF T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 91
... Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. DS70286A-page 89 ...
Page 92
... INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70286A-page 90 R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 R/W-0 R/W-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC3IF DMA21IF bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 93
... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. DS70286A-page 91 ...
Page 94
... C1IF: ECAN1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70286A-page 92 R/W-0 R/W-0 R/W-0 OC8IF OC7IF OC6IF R/W-0 R/W-0 R/W-0 DMA3IF C1IF C1RXIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC5IF IC6IF bit 8 R/W-0 R/W-0 SPI2IF SPI2EIF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 95
... Interrupt request has not occurred bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. DS70286A-page 93 ...
Page 96
... T7IF: Timer7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70286A-page 94 R/W-0 R/W-0 U-0 DCIIF DCIEIF — R/W-0 R/W-0 R/W-0 T9IF T8IF MI2C2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-0 — C2IF bit 8 R/W-0 R/W-0 SI2C2IF T7IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 97
... U2EIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 ...
Page 98
... T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70286A-page 96 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 R/W-0 R/W-0 DMA0IE T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 99
... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. DS70286A-page 97 ...
Page 100
... INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70286A-page 98 R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 R/W-0 R/W-0 INT1IE CNIE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC3IE DMA2IE bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 101
... Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. DS70286A-page 99 ...
Page 102
... C1IE: ECAN1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70286A-page 100 R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE R/W-0 R/W-0 R/W-0 DMA3IE C1IE C1RXIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC5IE IC6IE bit 8 R/W-0 R/W-0 SPI2IE SPI2EIE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 103
... Interrupt request enabled 0 = Interrupt request not enabled bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. DS70286A-page 101 ...
Page 104
... T7IE: Timer7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70286A-page 102 R/W-0 R/W-0 U-0 DCIIE DCIEIE — R/W-0 R/W-0 R/W-0 T9IE T8IE MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-0 — C2IE bit 8 R/W-0 R/W-0 SI2C2IE T7IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 105
... U2EIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-0 DMA6IE — ...
Page 106
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286A-page 104 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 107
... Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 108
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286A-page 106 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 109
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 110
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286A-page 108 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 111
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 112
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286A-page 110 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC4IP<2:0> bit 8 R/W-0 R/W-0 DMA2IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 113
... Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 114
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286A-page 112 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 C1RXIP<2:0> bit 8 R/W-0 R/W-0 SPI2EIP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 115
... Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 116
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286A-page 114 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC6IP<2:0> bit 8 R/W-0 R/W-0 IC6IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 117
... Unimplemented: Read as ‘0’ bit 2-0 OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ...
Page 118
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286A-page 116 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 MI2C2IP<2:0> bit 8 R/W-0 R/W-0 T7IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 119
... Unimplemented: Read as ‘0’ bit 2-0 T9IP<2:0>: Timer9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 120
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286A-page 118 R/W-0 U-0 U-0 — — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 C2IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 121
... Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DCIIP<2:0>: DCI Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...
Page 122
... Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70286A-page 120 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2EIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 123
... Unimplemented: Read as ‘0’ bit 2-0 DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 124
... Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70286A-page 122 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 125
... If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2007 Microchip Technology Inc. 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 126
... NOTES: DS70286A-page 124 © 2007 Microchip Technology Inc. ...
Page 127
... UART1 Reception UART1 Transmission UART2 Reception UART2 Transmission ADC1 ADC2 DCI ECAN1 Reception © 2007 Microchip Technology Inc. Peripheral ECAN1 Transmission ECAN2 Reception group ECAN2 Transmission The DMA controller features eight identical data transfer channels. Each channel has its own set of control and status registers ...
Page 128
... An additional pair of status registers, DMACS0 and DMACS1, are common to all DMAC channels. DS70286A-page 126 Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2007 Microchip Technology Inc. ...
Page 129
... Unimplemented: Read as ‘0’ bit 1-0 MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer Continuous, Ping-Pong modes enabled 01 = One-Shot, Ping-Pong modes disabled 00 = Continuous, Ping-Pong modes disabled © 2007 Microchip Technology Inc. R/W-0 R/W-0 U-0 HALF NULLW — ...
Page 130
... Please see Table 6-1 for a complete listing of IRQ numbers for all interrupt sources. DS70286A-page 128 U-0 U-0 U-0 — — R/W-0 U-0 U-0 (2) (2) (2) IRQSEL4 IRQSEL3 IRQSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) U-0 U-0 — — — bit 8 R/W-0 R/W-0 (2) (2) (2) IRQSEL1 IRQSEL0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 131
... DMAxSTB: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER B R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 STB<15:0>: Secondary DMA RAM Start Address bits (source or destination) © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 STA<15:8> R/W-0 R/W-0 R/W-0 STA<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 STB<15:8> R/W-0 ...
Page 132
... PAD<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (2) CNT<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 (2) CNT<9:8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 133
... No write collision detected bit 5 XWCOL5: Channel 5 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 4 XWCOL4: Channel 4 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected © 2007 Microchip Technology Inc. R/C-0 R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 R/C-0 R/C-0 ...
Page 134
... No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected DS70286A-page 132 © 2007 Microchip Technology Inc. ...
Page 135
... DMA2STB register selected 0 = DMA2STA register selected bit 1 PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMA1STB register selected 0 = DMA1STA register selected bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMA0STB register selected 0 = DMA0STA register selected © 2007 Microchip Technology Inc. U-0 R-1 R-1 — LSTCH<3:0> R-0 R-0 R-0 PPST4 ...
Page 136
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits DS70286A-page 134 R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 137
... SOSCO LPOSCEN SOSCI Note 1: See Figure 8-2 for PLL details © 2007 Microchip Technology Inc. • An on-chip PLL to scale the internal operating frequency to the required system clock frequency • The internal FRC oscillator can also be used with the PLL, thereby allowing full-speed operation without any external clock generation hardware • ...
Page 138
... MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F ’ is given by: OSC EQUATION 8-2: F OSC OSC IN © 2007 Microchip Technology Inc. is divided OSC ). are supported by the /2 OSC ’, IN CALCULATION ...
Page 139
... Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2007 Microchip Technology Inc. EQUATION 8-3: F OSC ...
Page 140
... OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete DS70286A-page 138 R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R/W-y R/W-y NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
Page 141
... PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-1 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE< ...
Page 142
... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 DS70286A-page 140 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 143
... Center frequency + 0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency – 0.375% (7.345 MHz) • • • 100001 = Center frequency – 11.625% (6.52 MHz) 100000 = Center frequency – 12% (6.49 MHz) © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 ...
Page 144
... Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. (OSCCON<5>) and the CF © 2007 Microchip Technology Inc. ...
Page 145
... Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2007 Microchip Technology Inc. mode stops clock operation and halts all code execu- tion. Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The ...
Page 146
... If a PMD bit is set, the corresponding mod- ule is disabled after a delay of 1 instruction cycle. Similarly PMD bit is cleared, the corresponding module is enabled after a delay of 1 instruction cycle (assuming the module control registers are already configured to enable module operation). © 2007 Microchip Technology Inc. possible ...
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... WR PORT CK Data Latch Read LAT Read Port © 2007 Microchip Technology Inc. When a peripheral is enabled and actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the group output driver for the parallel port bit will be disabled peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port ...
Page 148
... CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. in either Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. capable of detecting input © 2007 Microchip Technology Inc. ...
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... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2007 Microchip Technology Inc. • Interrupt on 16-bit Period register match or falling edge of external gate signal Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation Set the TON bit (= 1) in the T1CON register. ...
Page 150
... External clock from pin T1CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ DS70286A-page 148 U-0 U-0 — — R/W-0 U-0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 151
... For 32-bit timer/counter operation, Timer2, Timer4, Timer6 or Timer8 is the least significant word; Timer3, Timer5, Timer7 or Timer9 is the most significant word of the 32-bit timers. © 2007 Microchip Technology Inc. Note: For 32-bit operation, T3CON, T5CON, T7CON and T9CON control bits are ignored. Only T2CON, T4CON, T6CON and T8CON control bits are used for setup and control ...
Page 152
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70286A-page 150 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2007 Microchip Technology Inc. ...
Page 153
... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2007 Microchip Technology Inc. 1x Gate Sync TMR2 Sync Comparator PR2 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70286A-page 151 ...
Page 154
... Note 1: In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. DS70286A-page 152 U-0 U-0 — — R/W-0 R/W-0 (1) T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 155
... External clock from pin TyCK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON. © 2007 Microchip Technology Inc. U-0 U-0 (1) — — R/W-0 U-0 (1) — ...
Page 156
... NOTES: DS70286A-page 154 © 2007 Microchip Technology Inc. ...
Page 157
... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2007 Microchip Technology Inc. 2. Capture timer value on every edge (rising and falling) 3. Prescaler Capture Event modes -Capture timer value on every 4th rising edge ...
Page 158
... Timer selections may vary. Refer to the device data sheet for details. DS70286A-page 156 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 159
... To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to ‘100’. © 2007 Microchip Technology Inc. Disabling and re-enabling of the timer, and clearing the TMRy register, are not required but may be advantageous for defining a pulse from a known event time boundary ...
Page 160
... Table 14-1 shows example PWM frequencies and resolutions for a device operating at 10 MIPS log 10 F PWM log (2) 10 • (Timer2 Prescale Value) /F )/log 2) bits PWM 10 2) bits 10 CALCULATING THE PWM PERIOD • (Timer Prescale Value bits = 16 MHz and a Timer2 CY © 2007 Microchip Technology Inc. ...
Page 161
... Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the time bases associated with the module. Note: Only OC1 and OC2 can trigger a DMA data transfer. The corresponding TRISx bits must be cleared to configure the associated I/O pins as OC outputs. © 2007 Microchip Technology Inc 122 Hz 977 ...
Page 162
... Refer to the device data sheet for specific time bases available to the output compare module. DS70286A-page 160 U-0 U-0 U-0 — — — R-0 HC R/W-0 R/W-0 (1) OCFLT OCTSEL HS = Set in Hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 OCM<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 163
... Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer is com- pleted, the contents of the shift register (SPIxSR) are © 2007 Microchip Technology Inc. moved to the receive buffer. If any transmit data has been written to the buffer register, the contents of the transmit buffer are moved to SPIxSR ...
Page 164
... Sync Control Control Clock SDOx bit 0 SDIx SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF DS70286A-page 162 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer SPIxTXB Write SPIxBUF 16 Internal Data Bus 1:1/4/16/64 Primary F CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2007 Microchip Technology Inc. ...
Page 165
... User must write transmit data to/read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. FIGURE 15-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM dsPIC33F FIGURE 15-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM dsPIC33F © 2007 Microchip Technology Inc. PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer SDIx SDOx LSb ...
Page 166
... Invalid Invalid 10000 4:1 10000 5000 16:1 2500 1250 64:1 625 312.5 156.25 1:1 5000 2500 4:1 1250 625 16:1 313 156 64 4:1 6:1 8:1 6666.67 5000 2500 1666.67 1250 625 416.67 312.50 104.17 78.125 1250 833 625 313 208 156 © 2007 Microchip Technology Inc. ...
Page 167
... SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. © 2007 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 168
... The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). DS70286A-page 166 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE<2:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 PPRE<1:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 169
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application. © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — ...
Page 170
... NOTES: DS70286A-page 168 © 2007 Microchip Technology Inc. ...
Page 171
... I C master operation with 7 or 10-bit address For details about the communication sequence in each of these modes, please refer to the “dsPIC33F Family Reference Manual”. © 2007 Microchip Technology Inc Registers I2CxCON and I2CxSTAT are control and status registers, respectively. The I2CxCON register is readable and writable ...
Page 172
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2007 Microchip Technology Inc. ...
Page 173
... The control bit, IPMIEN, enables the module to support the Intelligent Peripheral Management Interface (IPMI). When this bit is set, the module accepts and acts upon all addresses. © 2007 Microchip Technology Inc. 16.8 General Call Address Support The general call address can address all devices. ...
Page 174
... SDAx is a ‘1’ and the data sampled on the SDAx pin = 0, then a bus collision has taken place. The 2 master will set the I C master events interrupt flag and 2 reset the master portion of the I C port to its Idle state. © 2007 Microchip Technology Inc. ...
Page 175
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2007 Microchip Technology Inc. R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 176
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress DS70286A-page 174 2 C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte master master master) © 2007 Microchip Technology Inc. ...
Page 177
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2007 Microchip Technology Inc. U-0 U-0 R/C-0 HS — — ...
Page 178
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70286A-page 176 2 C slave device address byte. © 2007 Microchip Technology Inc. ...
Page 179
... Unimplemented: Read as ‘0’ bit 9-0 AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2007 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 180
... NOTES: DS70286A-page 178 © 2007 Microchip Technology Inc. ...
Page 181
... UART1 or UART2 transmission or reception DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e., UTXISEL<1:0> and URXISEL<1:0> = 00). © 2007 Microchip Technology Inc. • Hardware Flow Control Option with UxCTS and UxRTS pins • Fully Integrated Baud Rate Generator with 16-bit Prescaler • ...
Page 182
... Desired Baud Rate UART BAUD RATE WITH BRGH = Baud Rate = 4 • (BRGx + BRGx = – • Baud Rate denotes the instruction cycle clock /2). OSC CY © 2007 Microchip Technology Inc. /4 ...
Page 183
... Write 0x55 to UxTXREG – loads Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2007 Microchip Technology Inc. 17.5 Receiving in 8-bit or 9-bit Data Mode 1. Set up the UART (as described in Section 17.2 “ ...
Page 184
... This feature is only available for the 16x BRG mode (BRGH = 0). 2: Bit availability depends on pin availability. DS70286A-page 182 MODE REGISTER x R/W-0 R/W-0 U-0 (1) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (2) R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 185
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is only available for the 16x BRG mode (BRGH = 0). 2: Bit availability depends on pin availability. © 2007 Microchip Technology Inc. MODE REGISTER (CONTINUED) x DS70286A-page 183 ...
Page 186
... Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). DS70286A-page 184 STATUS AND CONTROL REGISTER x U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R-0 R-1 UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 187
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). © 2007 Microchip Technology Inc. STATUS AND CONTROL REGISTER (CONTINUED) x DS70286A-page 185 ...
Page 188
... NOTES: DS70286A-page 186 © 2007 Microchip Technology Inc. ...
Page 189
... Signaling via interrupt capabilities for all CAN receiver and transmitter error states • Programmable clock source • Programmable link to input capture module (IC2 © 2007 Microchip Technology Inc. for both CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode The CAN bus module consists of a protocol engine and message buffering/control ...
Page 190
... RXF11 Filter RXF10 Filter RXF9 Filter RXF8 Filter RXF7 Filter RXF6 Filter RXF5 Filter RXF4 Filter RXF3 Filter RXF2 Filter RXF1 Filter RXF0 Filter Buffer RXM2 Mask RXM1 Mask RXM0 Mask Control CPU Configuration Bus Logic Interrupts © 2007 Microchip Technology Inc. ...
Page 191
... The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2<14>) enables or disables the filter. © 2007 Microchip Technology Inc. Note: Typically, if the CAN module is allowed to transmit in a particular mode of operation ...
Page 192
... Receiver Error Passive: The RXEP bit indicates that the receive error counter has exceeded the error passive limit of 127 and the module has gone into error passive state. © 2007 Microchip Technology Inc. ...
Page 193
... TXERRn bit will be set and the error condition may cause an interrupt. If the message loses arbitration during the transmission attempt, the TXLARBn bit is set. No interrupt is generated to signal the loss of arbitration. © 2007 Microchip Technology Inc. 18.5.4 AUTOMATIC PROCESSING OF REMOTE TRANSMISSION REQUESTS ...
Page 194
... By definition, the nominal bit time has a minimum and a maximum the minimum nominal bit time is 1 μsec corresponding to a maximum bit rate of 1 MHz. Phase Phase Segment 1 Segment 2 Sample Point . Also, by definition, Q Sync © 2007 Microchip Technology Inc. ...
Page 195
... CAN module allows the user to choose between sam- pling three times at the same point or once at the same point, by setting or clearing the SAM bit (CiCFG2<6>). © 2007 Microchip Technology Inc. Typically, the sampling of the bit should take place at about 60-70% through the bit time, depending on the system parameters ...
Page 196
... WIN: SFR Map Window Select bit 1 = Use filter window 0 = Use buffer window DS70286A-page 194 R/W-0 R/W-0 R/W-1 ABAT CANCKS U-0 R/W-0 U-0 — CANCAP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared CY OSC R/W-0 R/W-0 REQOP<2:0> bit 8 U-0 R/W-0 — — WIN bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 197
... Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up to data byte 3, bit 6 with EID<17> 00001 = Compare up to data byte 1, bit 7 with EID<0> 00000 = Do not compare data bytes © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — R-0 R-0 R-0 DNCNT< ...
Page 198
... TRB4 buffer interrupt 0000011 = TRB3 buffer interrupt 0000010 = TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt DS70286A-page 196 R-0 R-0 R-0 FILHIT<4:0> R-0 R-0 R-0 ICODE<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 199
... DMA RAM bit 12-5 Unimplemented: Read as ‘0’ bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = RB31 buffer 11110 = RB30 buffer . . . 00001 = TRB1 buffer 00000 = TRB0 buffer © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 FSA<4:0> Unimplemented bit, read as ‘0’ ...
Page 200
... FNRB<5:0>: FIFO Next Read Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer . . . 000001 = TRB1 buffer 000000 = TRB0 buffer DS70286A-page 198 R-0 R-0 R-0 FBP<5:0> R-0 R-0 R-0 FNRB<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...