S1D13700F02 Epson Electronics America, Inc., S1D13700F02 Datasheet - Page 82

• Manufacturer Part Number: S1D13700F02
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 82
12.2.3 Display Scan Timing
S1D13700F02
X42D-A-001-01
Frame
Period
Figure 12-7 Relationship Between Total Character Bytes Per Row and Character Bytes Per Row
Where:
C/R = character bytes per row (REG[03h] bits 7-0)
TC/R = total character bytes per row (REG[04h] bits 7-0)
L/F = frame height in lines (REG[05h] bits 7-0)
Note
During display scanning, the S1D13700F02 pauses at the end of each line for TC/R - C/R
((REG[04h] bits 7-0) - (REG[03h] bits 7-0)) display memory read cycles, although the
LCD drive signals are still generated. TC/R may be set to any value within the constraints
imposed by C/R, Input Clock (CLK), f
be used to fine tune the frame frequency.
The divider adjustment interval (R) applies to both the upper and lower screens even if a
dual panel drive is selected, REG[00h] bit 3 = 1. In this case, FPLINE is active only at
the end of the lower screen’s display interval.
FPLINE
Line 1
L/F
2
3
Revision 1.01
Display Period
C/R
FR
O
O
O
O
•
•
•
•
•
, and the size of the LCD panel. This pause may
TC/R
Epson Research and Development
Hardware Functional Specification
Divider Frequency
Vancouver Design Center
Issue Date: 2005/11/29
Period
R
R
R
R