S1D13700F02 Epson Electronics America, Inc., S1D13700F02 Datasheet - Page 16

• Manufacturer Part Number: S1D13700F02
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 16
5.2.1 Host Interface
S1D13700F02
X42D-A-001-01
Pin Name Type Pin #
CNF[1:0]
CNF[3:2]
A[15:1]
D[7:0]
CNF4
RD#
A0
IO
I
I
I
I
I
I
62-64,
44-47,
57, 56
59, 58
13-15
49-52
8-11,
2-6,
16
60
41
Many of the host interface pins have different functions depending on the selection of the
host bus interface (see configuration of CNF[4:2] pins in Table 5-6: “Summary of Config-
uration Options,” on page 20). For a summary of host interface pins, see Table 5-7: “Host
Interface Pin Mapping,” on page 21.
CB2
Cell
CI
CI
SI
SI
SI
SI
Table 5-2 Host Interface Pin Descriptions
HIOVDD
HIOVDD
HIOVDD
HIOVDD
HIOVDD
HIOVDD
HIOVDD
Power
Power On
RESET#/
State
—
—
—
—
—
—
Z
Revision 1.01
System Address pins 15-1.
System Address pin 0.
System data bus pins 7-0.
These tristate input/output data pins must be connected to the
microprocessor data bus.
These input pins are used for configuration of the FPSHIFT
clock cycle time and must be connected to either HIOVDD or
VSS. For further information, see Section 5.3, “Summary of
Configuration Options” on page 20.
These input pins select the host bus interface (microprocessor
interface) and must be connected to either HIOVDD or VSS.
The S1D13700F02 supports Generic processors (such as the
8085 and Z80®), the MC68K family of processors (such as the
68000) and the M6800 family of processors (such as the 6800).
For further information, see Section 5.3, “Summary of
Configuration Options” on page 20.
This input pin selects the microprocessor addressing mode and
must be connected to either HIOVDD or VSS. The
S1D13700F02 supports both Direct and Indirect addressing
modes. For further information, see Section 5.3, “Summary of
Configuration Options” on page 20.
This input pin has multiple functions.
• For Direct addressing mode, these pins are used for the
• For Indirect addressing mode, these pins must be
• For Direct addressing mode, this pin is used for system
• For Indirect addressing mode, this pin in conjunction with
• When the Generic host bus interface is selected, this pin is
• When the M6800 host bus interface is selected, this pin is
• When the MC68K host bus interface is selected, this pin is
system address bits 15-1.
connected to ground (VSS).
address bit 0.
RD# and WR# determines the type of data present on the
data bus.
the active-LOW read strobe (RD#). The S1D13700F02
data output buffers are enabled when this signal is low.
the active-high enable clock (E). Data is read from or
written to the S1D13700F02 when this clock goes high.
the active-low lower data strobe (LDS#). Data is read from
or written to the S1D13700F02 when this signal goes low.
Description
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 2005/11/29