S1D13700F02 Epson Electronics America, Inc., S1D13700F02 Datasheet - Page 41

• Manufacturer Part Number: S1D13700F02
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
9 Clocks
9.1 Clock Diagram
9.2 Clock Descriptions
9.2.1 System Clock
Hardware Functional Specification
Issue Date: 2005/11/29
FPSHIFT Cycle Time
(CNF[1:0] see Note)
Power Save Mode
(REG[08h] bit 0)
CLKI
Internal
OSC
Note
The following figure shows the clock tree of the S1D13700F02.
The maximum frequency of the system clock is 60MHz. The system clock source can be
either an external clock source (i.e. oscillator) or the internal oscillator (with external
crystal). If an external clock source is used, the crystal input (XCG1) must be pulled down
and the crystal output (XCD1) must be left unconnected. If the internal oscillator (with
external crystal) is used, the CLKI pin must be pulled down.
The FPSHIFT Cycle Time is configured using the CNF[1:0] pins. For further informa-
tion, see Section 5.3, “Summary of Configuration Options” on page 20.
System Clock
Figure 9-1: Clock Diagram
Revision 1.01
DIV
FPSHIFT Clock
X42D-A-001-01
S1D13700F02
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