S1D13700F02 Epson Electronics America, Inc., S1D13700F02 Datasheet - Page 100

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S1D13700F02

Manufacturer Part Number
S1D13700F02
Description
Embedded Memory Graphics Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

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Page 100
14 Microprocessor Interface
14.1 System Bus Interface
14.1.1 Generic
14.1.2 M6800 Family
14.1.3 MC68K Family
S1D13700F02
X42D-A-001-01
CNF[4:0], A[15:1], A0, D[7:0], RD#, WR#, AS and CS are used as control signals for the
microprocessor data bus. A0 is normally connected to the lowest bit of the system address
bus. CNF[4:2] change the operation of the RD# and WR# pins to enable interfacing to
either a Generic (Z80), M6800, or MC68K family bus, and should be pulled-up or pulled-
down according to Table 5-6: “Summary of Configuration Options,” on page 20.
The following table shows the signal states for each function.
The following table shows the signal states for each function.
The following table shows the signal states for each function.
A0
A0
A0
1
0
1
1
0
1
1
0
1
RD/WR# LDS#
R/W#
Table 14-2 M6800 Family Interface Signals
RD#
Table 14-3 MC68K Family Interface Signals
0
1
1
1
0
0
1
0
0
Table 14-1 Generic Interface Signals
WR#
1
0
0
E
1
1
1
0
0
0
Display data and cursor address read
Display data and parameter write
Command write
Display data and cursor address read
Display data and parameter write
Command write
Display data and cursor address read
Display data and parameter write
Command write
Revision 1.01
Function
Function
Function
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 2005/11/29

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