S1D13700F02 Epson Electronics America, Inc., S1D13700F02 Datasheet - Page 51

• Manufacturer Part Number: S1D13700F02
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
POWER SAVE
bit 0
Hardware Functional Specification
Issue Date: 2005/11/29
REG[08h] Power Save Mode Register
Address = 8008h
7
6
Default = 01h
Note
Note
Note
The POWER SAVE command is used to enter power save mode on the S1D13700F02
when indirect addressing is used. For further information on the POWER SAVE command,
see Section 11.1.2, “POWER SAVE” on page 71.
Power Save Mode Enable
This bit controls the state of the software initiated power save mode. When power save
mode is disabled, the S1D13700F02 is operating normally. When power save mode is
enabled, the S1D13700F02 is in a power efficient state where all internal operations,
including the oscillator, are stopped. For more information on the condition of the
S1D13700F02 during Power Save Mode, see Section 17, “Power Save Mode” on page
125.
When this bit = 0, power save mode is disabled (see note).
When this bit = 1, power save mode is enabled (default).
When indirect addressing is used, the SYSTEM SET command is used to exit power
save mode. For further information on the SYSTEM SET command, see Section 11.1.1,
“SYSTEM SET” on page 70.'
To fully disable power save mode when in Direct mode, a dummy write to any register
must be performed after setting REG[08h] bit 0 = 0.
Enabling power save mode automatically clears the Display Enable bit (REG[09h] bit
0). After power save mode is disabled, the Display Enable bit must be set (REG[09h] bit
0 = 1) in order to turn on the display again.
5
n/a
4
Revision 1.01
3
2
1
Power Save Mode
Read/Write
X42D-A-001-01
S1D13700F02
Enable
0
Page 51