S1D13700F02 Epson Electronics America, Inc., S1D13700F02 Datasheet - Page 21
S1D13700F02
Manufacturer Part Number
S1D13700F02
Description
Embedded Memory Graphics Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D13700F02.pdf
(130 pages)
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Vancouver Design Center
5.4 Host Bus Interface Pin Mapping
Hardware Functional Specification
Issue Date: 2005/11/29
Pin Name
CNF[1:0]
RESET#
A[15:1]
WAIT#
D[7:0]
CNF4
CNF3
CNF2
WR#
RD#
CS#
AS#
A0
Note
Connected to
Connected to
Connected to
Connected to
See Note
HIOVDD
RESET#
CNF[1:0] are used to configure the FPSHIFT cycle time and must be set according to
the requirements of the specific implementation.
Generic
WAIT# or Unconnected
A[15:1]
Direct
D[7:0]
WR#
CS#
RD#
VSS
VSS
VSS
A0
Table 5-7: Host Interface Pin Mapping
Connected to
Connected to
Connected to
Connected to
Connected to
See Note
HIOVDD
RESET#
HIOVDD
Generic
Indirect
D[7:0]
WR#
VSS
CS#
RD#
VSS
VSS
A0
Revision 1.01
Connected to
Connected to
Connected to
DTACK# or Unconnected
See Note
RD/WR#
RESET#
HIOVDD
HIOVDD
External
Decode
MC68K
A[15:1]
Direct
D[7:0]
LDS#
VSS
AS#
A0
Connected to
Connected to
Connected to
Connected to
See Note
RD/WR#
RESET#
HIOVDD
HIOVDD
HIOVDD
Indirect
External
Decode
MC68K
D[7:0]
LDS#
VSS
AS#
A0
M6800 Direct
supported
Not
Connected to
Connected to
Unconnected
Connected to
Connected to
Connected to
See Note
HIOVDD
RESET#
HIOVDD
HIOVDD
Indirect
External
Decode
M6800
D[7:0]
R/W#
VSS
VSS
A0
E
X42D-A-001-01
S1D13700F02
Page 21
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