S1D13700F02 Epson Electronics America, Inc., S1D13700F02 Datasheet - Page 25

• Manufacturer Part Number: S1D13700F02
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
7.2 Reset Timing
1. When using an external oscillator, a delay is required following the rising edges of both RESET# and VDD to
2. The
Hardware Functional Specification
Issue Date: 2005/11/29
RESET#
RESET#
allow for system stabilization. This delay allows the clock used by the internal oscillator circuit to become stable
before use. The LCDC must not be accessed before the oscillation circuit is stable.
When using the internal oscillator with an external crystal, a delay is required after exiting power save mode.
For direct mode, writing REG[08h] bit 0 will exit power save mode and start the internal oscillator.
For indirect mode, writing the SYSTEM SET command will exit power save mode and start the internal oscillator.
For maximum reliability, it is not recommended to apply a DC voltage to the LCD panel while the
is reset. Turn off the LCD power supplies for at least one frame period after the start of the reset pulse.
Note that during the reset period the
internal registers should be issued soon after a reset. During reset, the LCD drive signals FPDAT, FPLINE and
FR are halted.
V
V
Symbol
DD
DD
S1D13700F02
t1
t2
Oscillator stable delay (Note 1)
Reset pulse duration (Note 2)
Figure 7-3 Reset Timing When Using Internal Oscillator With External Crystal
Power Save Mode
t2
t2
requires a reset pulse of at least 1 ms after power-on in order to re-initialize its internal state.
0.3 V
Figure 7-2 Reset Timing When Using An External Oscillator
0.3 V
DD
DD
Parameter
t1
S1D13700F02
t1
Table 7-2 Reset Timing
Revision 1.01
Normal Mode
cannot receive commands. Commands to initialize the
Min
3
1
0.7 V
0.7 V
DD
DD
Power Save Mode
Max
⎯
⎯
t2
t2
0.3 V
0.3 V
S1D13700F02
Units
DD
DD
ms
ms
X42D-A-001-01
S1D13700F02
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