ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 68

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

Power saving modes
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Figure 29. Halt timing overview
1. A reset pulse of at least 42 µs must be applied when exiting from Halt mode.
Figure 30. Halt mode flowchart
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
5. The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.
Table 18: ST7LITE49K2 interrupt
during the interrupt routine and cleared when the CC register is popped.
[Active-halt disabled]
INSTRUCTION
RUN
N
HALT INSTRUCTION
WATCHDOG
(Active-halt disabled)
WDGHALT
HALT
mappingfor more details.
RESET
1
INTERRUPT
HALT
Y
1)
256 CPU CYCLE
ENABLE
3)
INTERRUPT
RESET
OR SERVICE INTERRUPT
0
256 CPU CLOCK CYCLE
FETCH RESET VECTOR
DELAY
OR
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BITS
N
DELAY
RESET
Y
WATCHDOG
VECTOR
FETCH
5)
DISABLE
2)
RUN
OFF
OFF
OFF
OFF
ON
ON
X
ON
ON
ON
X
0
4)
4)
ST7LITE49K2